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12 Open 22 Closed
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Issues list

Width cast of expression not propagating bug Something isn't working
#78 opened Jan 11, 2025 by dpetrisko
8
SVA (SystemVerilog assertions) support enhancement New feature or request
#77 opened Jan 10, 2025 by povik
1
Modules with assert property fail bug Something isn't working
#76 opened Jan 10, 2025 by 7FM
2
yosys-slang ignoring verilog_defaults enhancement New feature or request
#74 opened Jan 6, 2025 by dpetrisko
5
Simpler sourcing of technology libraries in FPGA flows enhancement New feature or request
#72 opened Dec 19, 2024 by gmsanchez
8
Feature unimplemented (xor X[N-1:0] (a, b, c)) enhancement New feature or request
#70 opened Dec 7, 2024 by miquelt9
1
Efficient handling of sparse memory initialization enhancement New feature or request
#69 opened Nov 21, 2024 by povik
Support ports w/o direct correspondence to a net/variable enhancement New feature or request
#67 opened Nov 2, 2024 by povik
1
lack of warnings/errors for unwanted latches enhancement New feature or request
#56 opened Oct 2, 2024 by astrollo
3
Failures in elaboration not caught in time bug Something isn't working
#50 opened Sep 13, 2024 by povik
Remove warning from the embedded cmake step enhancement New feature or request help wanted Extra attention is needed
#44 opened Sep 4, 2024 by povik
2
Emitting netlists with non-uniquified hierarchy enhancement New feature or request
#4 opened Jun 15, 2024 by povik
ProTip! Updated in the last three days: updated:>2025-01-10.