Modules with assert property fail

[7FM]

A simple module like:

module top    
    (
        input logic clk,
        input logic rst,
        input logic in,
        output logic out
    );

always_ff @(posedge clk) out <= in;

dummy_assertion:
    assert property (@(posedge clk) 1'b1);

endmodule

currently fails with the following message:

-- Running command `read_slang --ignore-timing --top top test/top.sv' --

1. Executing SLANG frontend.
Top level design units:
    top

test/top.sv:11:1: error: unsynthesizable timing control (ignore with '--ignore-timing')
dummy_assertion:
^

The option --ignore-timing does not affect the outcome.

Tested against the latest commit: 1b19302

[povik]

Thanks! This is a bug at least to the degree that it's a confusing error message. Let me check

[povik]

Let me fix the confusing error message, but as to the assert property syntax itself, that's part of SVA which is not supported at the moment. I've opened #77 to track