SVA (SystemVerilog assertions) support

[povik]

Support for SVA is missing, e.g. an assertion written in the following way is not supported as input:

  assert property (@(posedge clk) req |-> ##3 ack);

On the other hand plain assertions like

  always @(posedge clk) assert(/property/);

are supported.

[povik]

The SVA code in Verific importer is one lead for getting SVA support into yosys-slang: https://github.com/YosysHQ/yosys/blob/main/frontends/verific/verificsva.cc