Support zephyr for SOF on i.MX8ULP

boards/xtensa/nxp_adsp_imx8ulp/Kconfig.board

@@ -0,0 +1,7 @@
+# Xtensa board configuration
+
+# Copyright (c) 2023 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config  BOARD_NXP_ADSP_IMX8ULP
+	bool "NXP ADSP i.MX8ULP"

boards/xtensa/nxp_adsp_imx8ulp/Kconfig.defconfig

@@ -0,0 +1,10 @@
+# Copyright (c) 2023 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_NXP_ADSP_IMX8ULP
+
+config BOARD
+	default "nxp_adsp_imx8ulp"
+
+endif # BOARD_NXP_ADSP_IMX8ULP

boards/xtensa/nxp_adsp_imx8ulp/board.cmake

@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: Apache-2.0
+
+board_set_flasher_ifnset(misc-flasher)
+board_finalize_runner_args(misc-flasher)
+
+board_set_rimage_target(imx8ulp)

boards/xtensa/nxp_adsp_imx8ulp/nxp_adsp_imx8ulp.dts

@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2023 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <nxp/nxp_imx8ulp.dtsi>
+
+/ {
+	model = "nxp_adsp_imx8ulp";
+	compatible = "nxp";
+
+	chosen {
+		zephyr,sram = &sram0;
+	};
+};

boards/xtensa/nxp_adsp_imx8ulp/nxp_adsp_imx8ulp.yaml

@@ -0,0 +1,10 @@
+identifier: nxp_adsp_imx8ulp
+name: i.MX8ULP DSP
+type: mcu
+arch: xtensa
+toolchain:
+  - zephyr
+testing:
+  only_tags:
+    - kernel
+    - sof

boards/xtensa/nxp_adsp_imx8ulp/nxp_adsp_imx8ulp_defconfig

@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_SOC_SERIES_NXP_IMX8ULP=y
+CONFIG_SOC_NXP_IMX8ULP=y
+CONFIG_BOARD_NXP_ADSP_IMX8ULP=y
+
+CONFIG_BUILD_OUTPUT_BIN=n
+
+CONFIG_DYNAMIC_INTERRUPTS=y
+
+CONFIG_LOG=y

dts/xtensa/nxp/nxp_imx8ulp.dtsi

@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2023 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <xtensa/xtensa.dtsi>
+#include <mem.h>
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "cdns,tensilica-xtensa-lx7";
+			reg = <0>;
+		};
+	};
+
+	sram0: memory@8e000000 {
+		device_type = "memory";
+		compatible = "mmio-sram";
+		reg = <0x8e000000 DT_SIZE_K(512)>;
+	};
+
+	sram1: memory@8e800000 {
+		device_type = "memory";
+		compatible = "mmio-sram";
+		reg = <0x8e800000 DT_SIZE_K(512)>;
+	};
+};

scripts/west_commands/sign.py

@@ -441,7 +441,7 @@ def sign(self, command, build_dir, build_conf, formats):
         kernel_name = build_conf.get('CONFIG_KERNEL_BIN_NAME', 'zephyr')
 
         # TODO: make this a new sign.py --bootloader option.
-        if target in ('imx8', 'imx8m'):
+        if target in ('imx8', 'imx8m', 'imx8ulp'):
             bootloader = None
             kernel = str(b / 'zephyr' / f'{kernel_name}.elf')
             out_bin = str(b / 'zephyr' / f'{kernel_name}.ri')

soc/xtensa/nxp_adsp/imx8ulp/Kconfig.defconfig.series

@@ -0,0 +1,30 @@
+# Copyright (c) 2023 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_NXP_IMX8ULP
+
+config SOC_SERIES
+	string
+	default "imx8ulp"
+
+config SOC_TOOLCHAIN_NAME
+	string
+	default "nxp_imx8ulp_adsp"
+
+config SOC
+	string
+	default "nxp_imx8ulp"
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 528000000 if XTENSA_TIMER
+
+config SYS_CLOCK_TICKS_PER_SEC
+	default 50000
+
+config DCACHE_LINE_SIZE
+	default 128
+
+config GEN_IRQ_VECTOR_TABLE
+	default n
+
+endif # SOC_SERIES_NXP_IMX8ULP

soc/xtensa/nxp_adsp/imx8ulp/Kconfig.series

@@ -0,0 +1,15 @@
+# Copyright (c) 2023 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_NXP_IMX8ULP
+	bool "NXP i.MX8ULP Audio DSP Series"
+	select SOC_FAMILY_NXP_ADSP
+	select XTENSA
+	select XTENSA_HAL if ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" && "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xt-clang")
+	select XTENSA_RESET_VECTOR
+	select XTENSA_USE_CORE_CRT1
+	select ATOMIC_OPERATIONS_BUILTIN
+	select GEN_ISR_TABLES
+	select XTENSA_SMALL_VECTOR_TABLE_ENTRY
+	help
+	  Enable support for NXP i.MX8ULP Audio DSP

soc/xtensa/nxp_adsp/imx8ulp/Kconfig.soc

@@ -0,0 +1,11 @@
+# Copyright (c) 2023 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+choice
+	prompt "NXP i.MX8ULP Audio DSP Selection"
+	depends on SOC_SERIES_NXP_IMX8ULP
+
+	config SOC_NXP_IMX8ULP
+		bool "NXP i.MX8ULP Audio DSP"
+
+endchoice