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Brnch:master Trgt:chisel

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Matthew edited this page Feb 13, 2018 · 132 revisions

Time elapsed: 69 minutes, 32 seconds

Flags: --multifile=4 --synth

Results

Unit

Chisel.Unit.ArbitraryLambda: Pass
Chisel.Unit.BasicCondFSM: Pass
Chisel.Unit.BasicFSM: Pass
Chisel.Unit.BlockReduce1D: Pass
Chisel.Unit.BlockReduce2D: Pass
Chisel.Unit.Breakpoint: Pass
Chisel.Unit.BubbledWriteTest: Pass
Chisel.Unit.ChangingCtrMax: Pass
Chisel.Unit.CompactingFifo: Pass
Chisel.Unit.CtrlEnable: Pass
Chisel.Unit.DeviceMemcpy: Pass
Chisel.Unit.DiagBanking: Pass
Chisel.Unit.DotProductFSM: Pass
Chisel.Unit.FifoLoadSRAMStore: Pass
Chisel.Unit.FifoLoadStore: Pass
Chisel.Unit.FifoPushPop: Pass
Chisel.Unit.FifoStackFSM: Pass
Chisel.Unit.FixPtInOutArg: Pass
Chisel.Unit.FixPtMem: Pass
Chisel.Unit.FloatBasics: Pass
Chisel.Unit.IndirectLoad: Pass
Chisel.Unit.InOutArg: Pass
Chisel.Unit.LaneMaskPar: Pass
Chisel.Unit.LittleTypeTest: Pass
Chisel.Unit.LUTTest: Pass
Chisel.Unit.MaskedWrite: Pass
Chisel.Unit.Memcpy2D: Pass
Chisel.Unit.MemTest1D: Pass
Chisel.Unit.MemTest2D: Pass
Chisel.Unit.MixedIOTest: Pass
Chisel.Unit.MultiWriteBuffer: Pass
Chisel.Unit.Niter: Pass
Chisel.Unit.OHM: Pass
Chisel.Unit.PageBoundaryTest: Pass
Chisel.Unit.ParFifoLoad: Pass
Chisel.Unit.RetimedFifoBranch: Pass
Chisel.Unit.SequentialWrites: Pass
Chisel.Unit.SimpleFold: Pass
Chisel.Unit.SimpleMemReduce: Pass
Chisel.Unit.SimpleReduce: Pass
Chisel.Unit.SimpleSequential: Pass
Chisel.Unit.SimpleTileLoadStore: Pass
Chisel.Unit.SpecialMath: Pass
Chisel.Unit.SSV1D: Fail [Execution]
↳  Cause: Non-zero exit code
↳    See /home/mattfel/regression/testdir-master.2018-02-13_00-11-11.chisel.all/spatial-lang/logs/Chisel/Unit/SSV1D/make.log
Chisel.Unit.SSV2D: Pass
Chisel.Unit.StackLoadStore: Pass
Chisel.Unit.StridedLoad: Pass
Chisel.Unit.Tensor3D: Pass
Chisel.Unit.Tensor4D: Pass
Chisel.Unit.Tensor5D: Pass
Chisel.Unit.UnalignedFifoLoad: Pass
Chisel.Unit.UnalignedLd: Pass
Chisel.Unit.UnalignedTileLoadStore: Pass
Chisel.Unit.UniqueParallelLoad: Pass

Dense

Chisel.Dense.AES: Pass
Chisel.Dense.BlockReduce1D: Pass
Chisel.Dense.BTC: Pass
Chisel.Dense.Convolution_FPGA: Pass
Chisel.Dense.Differentiator: Pass
Chisel.Dense.DotProduct: Pass
Chisel.Dense.EdgeDetector: Pass
Chisel.Dense.FFT_Strided: Pass
Chisel.Dense.FFT_Transpose: Pass
Chisel.Dense.FixPtMem: Pass
Chisel.Dense.FloatBasics: Pass
Chisel.Dense.GDA: Pass
Chisel.Dense.GEMM_Blocked: Pass
Chisel.Dense.GEMM_NCubed: Pass
Chisel.Dense.Gibbs_Ising2D: Pass
Chisel.Dense.JPEG_Decompress: Pass
Chisel.Dense.JPEG_Markers: Pass
Chisel.Dense.Kmeans: Pass
Chisel.Dense.KMP: Pass
Chisel.Dense.MatMult_inner: Pass
Chisel.Dense.MatMult_outer: Pass
Chisel.Dense.MD_Grid: Pass
Chisel.Dense.MD_KNN: Pass
Chisel.Dense.MultiplexedWriteTest: Pass
Chisel.Dense.Niter: Pass
Chisel.Dense.NW: Pass
Chisel.Dense.OuterProduct: Pass
Chisel.Dense.SGD_minibatch: Pass
Chisel.Dense.SGD: Pass
Chisel.Dense.SHA1: Pass
Chisel.Dense.SimpleRowStridedConv: Pass
Chisel.Dense.Sobel: Pass
Chisel.Dense.Sort_Merge: Pass
Chisel.Dense.Sort_Radix: Pass
Chisel.Dense.SpecialMath: Pass
Chisel.Dense.Stencil2D: Pass
Chisel.Dense.Stencil3D: Pass
Chisel.Dense.SW: Pass
Chisel.Dense.SYRK_col: Pass
Chisel.Dense.Tensor3D: Pass
Chisel.Dense.Tensor4D: Pass
Chisel.Dense.Tensor5D: Pass
Chisel.Dense.TPCHQ6: Fail [Validation]
↳  Cause: Application reported that it did not pass validation.
Chisel.Dense.TRSM: Pass
Chisel.Dense.Viterbi: Pass

Sparse

Chisel.Sparse.BFS_Bulk: Pass
Chisel.Sparse.BFS_Queue: Pass

Fixme

Chisel.Fixme.Backprop: Pass
Chisel.Fixme.GatherStore: Fail [Execution]
↳  Cause: Execution timed out after 2000 seconds
Chisel.Fixme.PageRank_Bulk: Fail [Execution]
↳  Cause: Execution timed out after 2000 seconds
Chisel.Fixme.PageRank: Fail [Execution]
↳  Cause: Execution timed out after 2000 seconds
Chisel.Fixme.ScatterGather: Fail [Execution]
↳  Cause: Execution timed out after 2000 seconds
Chisel.Fixme.SPMV_CRS: Fail [Execution]
↳  Cause: Execution timed out after 2000 seconds
Chisel.Fixme.SPMV_DumbPack: Fail [Execution]
↳  Cause: Execution timed out after 2000 seconds
Chisel.Fixme.SPMV_ELL: Fail [Execution]
↳  Cause: Execution timed out after 2000 seconds

Performance Results

Pass Comments:

Commits

Spatial commit

commit 22e002de5efab826b30372ff598cca34dda7ad26
Merge: b460c66 262304f
Author: Matthew Feldman <[email protected]>
Date:   Tue Feb 13 00:11:04 2018 -0800

    Merge remote-tracking branch 'origin/pre-master'

commit 262304f14228cd6ee75bfc17b95d8ef8c400fe34
Merge: 715ffa4 4914675
Author: Matthew Feldman <[email protected]>
Date:   Mon Feb 12 23:55:16 2018 -0800

    Merge remote-tracking branch 'origin/develop' into retime

commit 491467540a64de0d33e2396fc5df00b9521da312
Author: Matthew Feldman <[email protected]>
Date:   Mon Feb 12 23:54:39 2018 -0800

    fix littletypetest and fix zcu hang

M	spatial/core/resources/models/StratixVLatency.csv
M	spatial/core/resources/models/UltraScalePlusLatency.csv
M	spatial/core/resources/models/ZynqLatency.csv
M	spatial/core/src/spatial/codegen/chiselgen/ChiselGenDRAM.scala

commit f89a7140a5e584a9a101dfc1814544e91caf03ae
Author: Matthew Feldman <[email protected]>
Date:   Mon Feb 12 23:23:37 2018 -0800

    make kmeans use more reasonable vcs args

M	apps

commit 715ffa45c0ab19e0daaebc265ed9fa208f2277f2
Merge: 29d367f 6148c30
Author: Matthew Feldman <[email protected]>
Date:   Mon Feb 12 18:28:28 2018 -0800

    Merge remote-tracking branch 'origin/develop' into retime

commit 6148c3055a8098fb12e1dc0cd0e2b1e77a90ea86
Author: Matthew Feldman <[email protected]>
Date:   Mon Feb 12 18:27:27 2018 -0800

    reverse bits for zynq/zcu unaligned. more debug regs in magcore. better printer in vcs

M	spatial/core/resources/chiselgen/template-level/fringeHW/MAGCore.scala
M	spatial/core/resources/chiselgen/template-level/fringeHW/MAGToAXI4Bridge.scala
M	spatial/core/resources/cppgen/fringeVCS/FringeContextVCS.h

commit 5695c10dd0f10e8442fdfc71a1c49e6c7e181519
Author: Matthew Feldman <[email protected]>
Date:   Mon Feb 12 17:24:33 2018 -0800

    fix zcu in many places

M	apps
M	argon
M	spatial/core/resources/chiselgen/template-level/fringeHW/FIFOWidthConvert.scala
M	spatial/core/resources/chiselgen/template-level/fringeHW/FringeBundles.scala
M	spatial/core/resources/chiselgen/template-level/fringeHW/MAGCore.scala
M	spatial/core/resources/chiselgen/template-level/fringeHW/axi4/Bundles.scala
M	spatial/core/resources/chiselgen/template-level/fringeVCS/DRAM.h
M	spatial/core/src/spatial/codegen/chiselgen/ChiselGenDRAM.scala

commit dfe770f8c44d03556d740997cdba50bbafba3c0e
Author: Matthew Feldman <[email protected]>
Date:   Mon Feb 12 14:24:24 2018 -0800

    fix unaligend strb

M	spatial/core/resources/chiselgen/template-level/fringeHW/MAGCore.scala

commit 4834c8ccb95d111fff234fb72cd3784756cbdac8
Author: Matthew Feldman <[email protected]>
Date:   Mon Feb 12 14:06:17 2018 -0800

    safer check for unalignedstores DLI patch

M	spatial/core/src/spatial/codegen/chiselgen/ChiselGenDRAM.scala

commit e7fc9ae912f690cfdd397cb5967a1da6018fd6ca
Author: Matthew Feldman <[email protected]>
Date:   Mon Feb 12 14:00:28 2018 -0800

    fix asic compile errors

M	argon
M	spatial/core/resources/chiselgen/app-level/Top.scala
M	spatial/core/resources/chiselgen/template-level/fringeASIC/build/RetimeShiftRegister.sv
M	spatial/core/resources/chiselgen/template-level/fringeHW/Fringe.scala
M	spatial/core/resources/chiselgen/template-level/fringeHW/MAGCore.scala

commit 9c75d9707ba187ba9babbda69f5094d15965a481
Author: Matthew Feldman <[email protected]>
Date:   Mon Feb 12 10:53:29 2018 -0800

    fix ready delay line holder issues and explicitly add DLI to fringestore

M	spatial/core/src/spatial/codegen/chiselgen/ChiselGenDRAM.scala
M	spatial/core/src/spatial/codegen/chiselgen/ChiselGenSRAM.scala

commit 345a7be58ef359d84fa314a842060b538bb0fe13
Author: Matthew Feldman <[email protected]>
Date:   Sun Feb 11 21:48:16 2018 -0800

    unify fpga with plasticine tilestore once again, fix issues with vcs wdata coming before wcmd or multiple coming without being serviced

M	spatial/core/resources/chiselgen/template-level/fringeVCS/DRAM.h
M	spatial/core/resources/chiselgen/template-level/fringeVCS/Top-harness.sv
M	spatial/core/resources/cppgen/fringeVCS/FringeContextVCS.h
M	spatial/core/src/spatial/lang/DRAMTransfersInternal.scala

commit 7f97195658299a42dfec560ebd8210c0d97e8d6e
Author: Matthew Feldman <[email protected]>
Date:   Sun Feb 11 12:38:37 2018 -0800

    check regression_env properly

M	spatial/core/resources/chiselgen/app-level/Makefile

commit b50d72e217626a077a0582a99002565fd6c3e963
Author: Matthew Feldman <[email protected]>
Date:   Sun Feb 11 12:27:42 2018 -0800

    move sparse apps to fixme

M	apps

commit 7eea638bdbbc73656bfdf80d9b22facddee04fcb
Author: Matthew Feldman <[email protected]>
Date:   Sun Feb 11 12:23:09 2018 -0800

    force vcd off during regresion (properly), fix wstrb connectino in bd

M	spatial/core/resources/chiselgen/app-level/Makefile
M	spatial/core/resources/chiselgen/app-level/scripts/regression_run.sh
M	spatial/core/resources/chiselgen/template-level/fringeZynq/build/bdproject.tcl
M	spatial/core/src/spatial/lang/DRAMTransfersInternal.scala
M	utilities/receive.sh
M	utilities/synth_launcher.sh

commit 32df181daaaf59d09d80d0beb1ee89ab9e16dbd0
Author: Matthew Feldman <[email protected]>
Date:   Sat Feb 10 23:54:43 2018 -0800

    fix fifocore sram with floating addr if size=1 and turn off waveforms for regression

M	spatial/core/resources/chiselgen/app-level/scripts/regression_run.sh
M	spatial/core/resources/chiselgen/template-level/fringeHW/FIFOCore.scala

commit 110b59b7e4c93ee66e015c01ede48cfe1f7ae043
Author: Matthew Feldman <[email protected]>
Date:   Sat Feb 10 23:12:44 2018 -0800

    fix scattergather compile crash but didnt fix their hang

M	spatial/core/resources/chiselgen/template-level/fringeHW/MAGCore.scala

commit fb93128735d1e38edef1006de20f1dfdac1b4f9b
Author: Matthew Feldman <[email protected]>
Date:   Sat Feb 10 14:27:15 2018 -0800

    fix some compile crashes

M	argon
M	spatial/core/resources/chiselgen/template-level/fringeHW/MAGCore.scala
M	spatial/core/resources/chiselgen/template-level/fringeZynq/build/bdproject.tcl
M	spatial/core/src/spatial/codegen/chiselgen/ChiselGenDRAM.scala

commit 29d367f56aaa4bc9970c73e50fbc38046c6a3ba5
Merge: 755e3b8 fff7591
Author: Matthew Feldman <[email protected]>
Date:   Sat Feb 10 13:05:53 2018 -0800

    Merge remote-tracking branch 'origin/develop' into retime

commit fff75913c501ea2abb599cd2a6ead3b5751f78e9
Author: Matthew Feldman <[email protected]>
Date:   Sat Feb 10 13:03:33 2018 -0800

    connect accel strobe to fringe strobe to dram strobe

M	apps
M	spatial/core/resources/chiselgen/template-level/fringeHW/FIFOArbiter.scala
M	spatial/core/resources/chiselgen/template-level/fringeHW/FIFOWidthConvert.scala
M	spatial/core/resources/chiselgen/template-level/fringeHW/MAGCore.scala
M	spatial/core/resources/chiselgen/template-level/fringeHW/MAGToAXI4Bridge.scala
M	spatial/core/resources/chiselgen/template-level/fringeHW/MuxN.scala
M	spatial/core/resources/chiselgen/template-level/fringeHW/RegFile.scala
M	spatial/core/resources/chiselgen/template-level/fringeVCS/DRAM.h
A	spatial/core/resources/chiselgen/template-level/fringeZynq/build/AXI4LiteToRFBridgeZCUVerilog.v
M	spatial/core/src/spatial/codegen/chiselgen/ChiselGenDRAM.scala

commit 755e3b80aba22d6b1677eaa0209a478d4fb6f1ad
Merge: 90e11c6 b57ee51
Author: Matthew Feldman <[email protected]>
Date:   Sat Feb 10 09:12:32 2018 -0800

    Merge remote-tracking branch 'origin/develop' into retime

commit b57ee5142739832a38590b81f654eb3f3ba1c807
Merge: d839c5c 2cecbf6
Author: Matthew Feldman <[email protected]>
Date:   Sat Feb 10 09:12:01 2018 -0800

    develop automerge

commit 2cecbf6ff12066e831e5c622fbf3fd07c3708aeb
Author: Matthew Feldman <[email protected]>
Date:   Fri Feb 9 20:12:23 2018 -0800

    update argon too

M	argon

commit 76ccdaa36ce9b3ae91f4866926c2d8f345a3798d
Author: Matthew Feldman <[email protected]>
Date:   Fri Feb 9 20:12:09 2018 -0800

    fix zcu to the best of my ability and start support for unaligned stores

M	spatial/core/resources/chiselgen/app-level/Top.scala
M	spatial/core/resources/chiselgen/template-level/fringeHW/FIFOWidthConvert.scala
M	spatial/core/resources/chiselgen/template-level/fringeHW/Fringe.scala
M	spatial/core/resources/chiselgen/template-level/fringeHW/FringeBundles.scala
M	spatial/core/resources/chiselgen/template-level/fringeHW/FringeZynq.scala
M	spatial/core/resources/chiselgen/template-level/fringeHW/MAGCore.scala
M	spatial/core/resources/chiselgen/template-level/fringeHW/RegFile.scala
M	spatial/core/resources/chiselgen/template-level/fringeVCS/DRAM.h
M	spatial/core/resources/chiselgen/template-level/fringeVCS/Top-harness.sv
M	spatial/core/resources/chiselgen/template-level/fringeZynq/build/bdproject.tcl
M	spatial/core/resources/cppgen/fringeZCU/FringeContextZCU.h
M	spatial/core/src/spatial/codegen/chiselgen/ChiselGenDRAM.scala
M	utilities/synth_regression.sh

commit d839c5cdeb420e1df83126f7903a615e51e450ad
Author: Matthew Vilim <[email protected]>
Date:   Tue Jan 30 14:42:29 2018 -0800

    retime Fringe

M	spatial/core/resources/chiselgen/template-level/fringeHW/Counter.scala
M	spatial/core/resources/chiselgen/template-level/fringeHW/Depulser.scala
M	spatial/core/resources/chiselgen/template-level/fringeHW/FF.scala
M	spatial/core/resources/chiselgen/template-level/fringeHW/FIFOArbiter.scala
M	spatial/core/resources/chiselgen/template-level/fringeHW/FIFOCore.scala
M	spatial/core/resources/chiselgen/template-level/fringeHW/MAGCore.scala
M	spatial/core/resources/chiselgen/template-level/fringeHW/MuxN.scala
M	spatial/core/resources/chiselgen/template-level/fringeHW/RegFile.scala
M	spatial/core/resources/chiselgen/template-level/fringeHW/UpDownCtr.scala
M	spatial/core/resources/chiselgen/template-level/templates/SRAM.scala
M	spatial/core/resources/chiselgen/template-level/templates/Utils.scala
M	spatial/core/src/spatial/codegen/chiselgen/ChiselGenSRAM.scala

commit 20a19c4a0c6d585970bc762dbdd4d18701e4305a
Author: Matthew Feldman <[email protected]>
Date:   Thu Feb 8 11:39:55 2018 -0800

    fix viterbi segfault on zynq

M	spatial/core/resources/cppgen/fringeZynq/FringeContextZynq.h

Argon commit

commit 6d3d2e24f37f6a2ac8ebd0cdb978c6aa2688e366
Author: Matthew Feldman <[email protected]>
Date:   Mon Feb 12 17:21:47 2018 -0800

    fix dumb mistake with 64 bit axi bus in zcu

M	core/src/argon/codegen/chiselgen/ChiselFileGen.scala

Virtualized commit

commit 1a5adc8e9cd171f1a8c3f1f66dddbc04d89aa51f
Author: David Koeplinger <[email protected]>
Date:   Fri Jul 21 17:15:08 2017 -0700

    fix mistake in Structs

M	src/org/virtualized/Structs.scala

Spatial-Apps commit

commit c4cf67ffd9fc0ef30e74fb0dd4147a887b16c865
Author: Matthew Feldman <[email protected]>
Date:   Mon Feb 12 23:23:27 2018 -0800

    make kmeans use vcs args instead of board args...

M	src/Regression.scala

Test summary

Creation Time- 2018-02-13_00-11-11 | Status- debug | Type- chisel | tests- all | User- mattfel | Origin- london | Destination- tucson | Branch- master | Spatial- 22e00 | Argon- 6d3d2 | Virtualized- 1a5ad | Spatial-apps- c4cf6

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