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Issues: stanford-ppl/spatial-lang

56 Open 194 Closed
56 Open 194 Closed
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Issues list

Aligned load becomes unaligned load because of type conversion bug
#264 opened May 18, 2018 by yaqiz01
@dkoeplin @mattfel1
Reduction with 0 loop iterations is not well defined bug enhancement
#263 opened Apr 17, 2018 by dkoeplin
@dkoeplin
5
Moving to [SGN, WIDTH, OFFSET] Representation for FixPt
#261 opened Feb 26, 2018 by mattfel1
1
API for unbiased and saturating casting
#260 opened Feb 22, 2018 by mattfel1
1
Cat API
#258 opened Feb 13, 2018 by mattfel1
1
Proper Control Flow for FIR filter
#257 opened Jan 25, 2018 by mattfel1
Warn or Error if Trying to Read to ArgOut in Accel
#255 opened Jan 17, 2018 by mattfel1
3
Implement Spatial ILA for On-Board Waveform Debugging enhancement
#253 opened Jan 12, 2018 by mattfel1
3
AWS Fringe: Support 4 DRAM Channels
#249 opened Nov 29, 2017 by shadjis
@raghup17 @shadjis
Throw warning for parallelized, unaligned loads into LineBuffer or rethink template
#246 opened Nov 26, 2017 by mattfel1
Latched Values of RegFile over AXI
#239 opened Nov 1, 2017 by mattfel1
Mux between memories
#237 opened Oct 25, 2017 by mattfel1
Use MACC IP
#232 opened Oct 4, 2017 by shadjis
@raghup17 @dkoeplin
@mattfel1 @shadjis
3
Improve ultra ram width utilization
#231 opened Oct 4, 2017 by shadjis
@raghup17 @dkoeplin
@mattfel1 @shadjis
Use URAMs on F1
#230 opened Oct 4, 2017 by shadjis
@raghup17 @dkoeplin
@mattfel1 @shadjis
6
Naughty Usage of LineBuffer, Should We Throw Warning?
#228 opened Sep 28, 2017 by mattfel1
Banking and Dispatch Strangeness
#226 opened Sep 20, 2017 by mattfel1
Use real latencies for compacting fifos
#221 opened Sep 8, 2017 by mattfel1
@mattfel1
AccessDispatch has more than one dispatch
#220 opened Sep 7, 2017 by mattfel1
@dkoeplin @mattfel1 @shadjis
2
Updates for Plasticine enhancement
#219 opened Aug 29, 2017 by dkoeplin
6 of 9 tasks
@dkoeplin
6
Systolic Array support enhancement
#218 opened Aug 29, 2017 by mattfel1
@dkoeplin @mattfel1
Cheaper SRAM
#217 opened Aug 29, 2017 by mattfel1
@mattfel1
Load/Store on part of struct discuss enhancement
#212 opened Aug 22, 2017 by mattfel1
1
II for Innerpipe FSM Wrong awaiting test bug
#204 opened Aug 4, 2017 by mattfel1
@dkoeplin
2
RegFile load/store chunks from/to SRAM enhancement
#185 opened Jul 23, 2017 by rubenfiszel
@dkoeplin
ProTip! Exclude everything labeled bug with -label:bug.