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Brnch:master Trgt:chisel
Time elapsed: 64 minutes, 44 seconds
Flags: --multifile=4 --synth
Chisel.Unit.ArbitraryLambda: Pass
Chisel.Unit.BasicCondFSM: Pass
Chisel.Unit.BasicFSM: Pass
Chisel.Unit.BlockReduce1D: Pass
Chisel.Unit.BlockReduce2D: Pass
Chisel.Unit.Breakpoint: Pass
Chisel.Unit.BubbledWriteTest: Pass
Chisel.Unit.ChangingCtrMax: Pass
Chisel.Unit.CompactingFifo: Pass
Chisel.Unit.CtrlEnable: Pass
Chisel.Unit.DeviceMemcpy: Pass
Chisel.Unit.DiagBanking: Pass
Chisel.Unit.DotProductFSM: Pass
Chisel.Unit.FifoLoadSRAMStore: Pass
Chisel.Unit.FifoLoadStore: Pass
Chisel.Unit.FifoPushPop: Pass
Chisel.Unit.FifoStackFSM: Pass
Chisel.Unit.FixPtInOutArg: Pass
Chisel.Unit.FixPtMem: Pass
Chisel.Unit.FloatBasics: Pass
Chisel.Unit.IndirectLoad: Pass
Chisel.Unit.InOutArg: Pass
Chisel.Unit.LaneMaskPar: Pass
Chisel.Unit.LittleTypeTest: Pass
Chisel.Unit.LUTTest: Pass
Chisel.Unit.MaskedWrite: Pass
Chisel.Unit.Memcpy2D: Pass
Chisel.Unit.MemTest1D: Pass
Chisel.Unit.MemTest2D: Pass
Chisel.Unit.MixedIOTest: Pass
Chisel.Unit.MultiWriteBuffer: Pass
Chisel.Unit.Niter: Pass
Chisel.Unit.OHM: Pass
Chisel.Unit.PageBoundaryTest: Pass
Chisel.Unit.ParFifoLoad: Pass
Chisel.Unit.RetimedFifoBranch: Pass
Chisel.Unit.SequentialWrites: Pass
Chisel.Unit.SimpleFold: Pass
Chisel.Unit.SimpleMemReduce: Pass
Chisel.Unit.SimpleReduce: Pass
Chisel.Unit.SimpleSequential: Pass
Chisel.Unit.SimpleTileLoadStore: Pass
Chisel.Unit.SmallTensorLoad: Pass
Chisel.Unit.SpecialMath: Pass
Chisel.Unit.SSV1D: Pass
Chisel.Unit.SSV2D: Pass
Chisel.Unit.StackLoadStore: Pass
Chisel.Unit.StridedLoad: Pass
Chisel.Unit.Tensor3D: Pass
Chisel.Unit.Tensor4D: Pass
Chisel.Unit.Tensor5D: Pass
Chisel.Unit.UnalignedFifoLoad: Pass
Chisel.Unit.UnalignedLd: Pass
Chisel.Unit.UnalignedTileLoadStore: Pass
Chisel.Unit.UniqueParallelLoad: Pass
Chisel.Dense.AES: Pass
Chisel.Dense.BlockReduce1D: Pass
Chisel.Dense.BTC: Pass
Chisel.Dense.Convolution_FPGA: Pass
Chisel.Dense.Differentiator: Pass
Chisel.Dense.DotProduct: Pass
Chisel.Dense.EdgeDetector: Pass
Chisel.Dense.FFT_Strided: Pass
Chisel.Dense.FFT_Transpose: Pass
Chisel.Dense.FixPtMem: Pass
Chisel.Dense.FloatBasics: Pass
Chisel.Dense.GDA: Pass
Chisel.Dense.GEMM_Blocked: Pass
Chisel.Dense.GEMM_NCubed: Pass
Chisel.Dense.Gibbs_Ising2D: Pass
Chisel.Dense.JPEG_Decompress: Pass
Chisel.Dense.JPEG_Markers: Pass
Chisel.Dense.Kmeans: Pass
Chisel.Dense.KMP: Pass
Chisel.Dense.MatMult_inner: Pass
Chisel.Dense.MatMult_outer: Pass
Chisel.Dense.MD_Grid: Pass
Chisel.Dense.MD_KNN: Pass
Chisel.Dense.MultiplexedWriteTest: Pass
Chisel.Dense.Niter: Pass
Chisel.Dense.NW: Pass
Chisel.Dense.OuterProduct: Pass
Chisel.Dense.SGD_minibatch: Pass
Chisel.Dense.SGD: Pass
Chisel.Dense.SHA1: Pass
Chisel.Dense.SimpleRowStridedConv: Pass
Chisel.Dense.Sobel: Pass
Chisel.Dense.Sort_Merge: Fail [Execution]
↳ Cause: Execution timed out after 2000 seconds
Chisel.Dense.Sort_Radix: Pass
Chisel.Dense.SpecialMath: Pass
Chisel.Dense.Stencil2D: Pass
Chisel.Dense.Stencil3D: Pass
Chisel.Dense.SW: Pass
Chisel.Dense.SYRK_col: Pass
Chisel.Dense.Tensor3D: Pass
Chisel.Dense.Tensor4D: Pass
Chisel.Dense.Tensor5D: Pass
Chisel.Dense.TPCHQ6: Pass
Chisel.Dense.TRSM: Pass
Chisel.Dense.Viterbi: Pass
Chisel.Sparse.BFS_Bulk: Pass
Chisel.Sparse.BFS_Queue: Pass
Chisel.Sparse.GatherStore: Pass
Chisel.Sparse.PageRank_Bulk: Pass
Chisel.Sparse.PageRank: Pass
Chisel.Sparse.ScatterGather: Pass
Chisel.Sparse.SPMV_CRS: Pass
Chisel.Sparse.SPMV_ELL: Pass
Chisel.Fixme.Backprop: Pass
Spatial commit
commit f21c1bdc5b281a89c43034c99f477388ac0db60b
Merge: 9168ead 81c3827
Author: Matthew Feldman <[email protected]>
Date: Sat Feb 17 20:09:29 2018 -0800
Merge remote-tracking branch 'origin/pre-master'
commit 81c38278a40165f027b3f7482ae47e8cf9e31c83
Merge: cbf8182 70d38cc
Author: Matthew Feldman <[email protected]>
Date: Sat Feb 17 20:09:11 2018 -0800
Merge remote-tracking branch 'origin/syncMem' into pre-master
commit 70d38ccb8eaf51857b234af9054becda080f9397
Merge: 864b7ec 91bdda1
Author: Matthew Feldman <[email protected]>
Date: Sat Feb 17 20:08:34 2018 -0800
Merge remote-tracking branch 'origin/develop' into retime
commit 91bdda1d3e59cc4e21a6797cbb4df5eb0e5a0f6f
Merge: aef37bd 1802e9d
Author: Matthew Feldman <[email protected]>
Date: Sat Feb 17 20:08:15 2018 -0800
Merge remote-tracking branch 'origin/fpga' into develop
commit 1802e9d871aecc89e84bec05de50d1bb206ccf8f
Author: Matthew Feldman <[email protected]>
Date: Sat Feb 17 20:07:52 2018 -0800
fix hang if done occurs on the same cycle that ready turns off, which would cause a hang in dram stores because innerpipe would go to the donestate preemptively and streamCatchDone would trigger a cycle too soon
M spatial/core/resources/chiselgen/template-level/fringeHW/MAGCore.scala
M spatial/core/resources/chiselgen/template-level/templates/Innerpipe.scala
M spatial/core/resources/chiselgen/template-level/templates/Utils.scala
Argon commit
commit 6d3d2e24f37f6a2ac8ebd0cdb978c6aa2688e366
Author: Matthew Feldman <[email protected]>
Date: Mon Feb 12 17:21:47 2018 -0800
fix dumb mistake with 64 bit axi bus in zcu
M core/src/argon/codegen/chiselgen/ChiselFileGen.scala
Virtualized commit
commit 1a5adc8e9cd171f1a8c3f1f66dddbc04d89aa51f
Author: David Koeplinger <[email protected]>
Date: Fri Jul 21 17:15:08 2017 -0700
fix mistake in Structs
M src/org/virtualized/Structs.scala
Spatial-Apps commit
commit 30d3028bb00501d13c5af904e12b69cd4e70da06
Author: Matthew Feldman <[email protected]>
Date: Fri Feb 16 17:07:46 2018 -0800
?
M src/Regression.scala
Creation Time- 2018-02-17_20-09-35 | Status- debug | Type- chisel | tests- all | User- mattfel | Origin- london | Destination- tucson | Branch- master | Spatial- f21c1 | Argon- 6d3d2 | Virtualized- 1a5ad | Spatial-apps- 30d30