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Brnch:master Trgt:chisel

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Matthew edited this page Jan 31, 2018 · 132 revisions

Time elapsed: 81 minutes, 48 seconds

Flags: --multifile=5 --synth

Results

Unit

Chisel.Unit.ArbitraryLambda: Pass
Chisel.Unit.BasicCondFSM: Pass
Chisel.Unit.BasicFSM: Pass
Chisel.Unit.BlockReduce1D: Pass
Chisel.Unit.BlockReduce2D: Pass
Chisel.Unit.Breakpoint: Pass
Chisel.Unit.BubbledWriteTest: Pass
Chisel.Unit.ChangingCtrMax: Pass
Chisel.Unit.CompactingFifo: Pass
Chisel.Unit.CtrlEnable: Pass
Chisel.Unit.DeviceMemcpy: Pass
Chisel.Unit.DiagBanking: Pass
Chisel.Unit.DotProductFSM: Pass
Chisel.Unit.FifoLoadSRAMStore: Pass
Chisel.Unit.FifoLoadStore: Pass
Chisel.Unit.FifoPushPop: Pass
Chisel.Unit.FifoStackFSM: Pass
Chisel.Unit.FixPtInOutArg: Pass
Chisel.Unit.FixPtMem: Pass
Chisel.Unit.FloatBasics: Pass
Chisel.Unit.IndirectLoad: Pass
Chisel.Unit.InOutArg: Pass
Chisel.Unit.LaneMaskPar: Pass
Chisel.Unit.LUTTest: Pass
Chisel.Unit.MaskedWrite: Pass
Chisel.Unit.Memcpy2D: Pass
Chisel.Unit.MemTest1D: Pass
Chisel.Unit.MemTest2D: Pass
Chisel.Unit.MixedIOTest: Pass
Chisel.Unit.MultiplexedWriteTest: Pass
Chisel.Unit.MultiWriteBuffer: Pass
Chisel.Unit.Niter: Pass
Chisel.Unit.OHM: Pass
Chisel.Unit.PageBoundaryTest: Pass
Chisel.Unit.ParFifoLoad: Pass
Chisel.Unit.RetimedFifoBranch: Pass
Chisel.Unit.SequentialWrites: Pass
Chisel.Unit.SimpleFold: Pass
Chisel.Unit.SimpleMemReduce: Pass
Chisel.Unit.SimpleReduce: Pass
Chisel.Unit.SimpleSequential: Pass
Chisel.Unit.SimpleTileLoadStore: Pass
Chisel.Unit.SpecialMath: Pass
Chisel.Unit.SSV1D: Pass
Chisel.Unit.SSV2D: Pass
Chisel.Unit.StackLoadStore: Pass
Chisel.Unit.StridedLoad: Pass
Chisel.Unit.Tensor3D: Pass
Chisel.Unit.Tensor4D: Pass
Chisel.Unit.Tensor5D: Pass
Chisel.Unit.UnalignedFifoLoad: Pass
Chisel.Unit.UnalignedLd: Pass
Chisel.Unit.UniqueParallelLoad: Pass

Dense

Chisel.Dense.AES: Pass
Chisel.Dense.BasicBLAS: Pass
Chisel.Dense.BTC: Pass
Chisel.Dense.Convolution_FPGA: Pass
Chisel.Dense.Convolutions: Fail [Validation]
↳  Cause: Application reported that it did not pass validation.
Chisel.Dense.Differentiator: Pass
Chisel.Dense.DotProduct: Pass
Chisel.Dense.EdgeDetector: Pass
Chisel.Dense.FFT_Strided: Pass
Chisel.Dense.FFT_Transpose: Pass
Chisel.Dense.GDA: Pass
Chisel.Dense.GEMM_Blocked: Pass
Chisel.Dense.GEMM_NCubed: Pass
Chisel.Dense.Gibbs_Ising2D: Pass
Chisel.Dense.JPEG_Decompress: Pass
Chisel.Dense.JPEG_Markers: Pass
Chisel.Dense.Kmeans: Pass
Chisel.Dense.KMP: Pass
Chisel.Dense.MatMult_inner: Pass
Chisel.Dense.MatMult_outer: Pass
Chisel.Dense.MD_Grid: Pass
Chisel.Dense.MD_KNN: Pass
Chisel.Dense.NW: Pass
Chisel.Dense.OuterProduct: Pass
Chisel.Dense.SGD_minibatch: Pass
Chisel.Dense.SGD: Pass
Chisel.Dense.SHA1: Pass
Chisel.Dense.SimpleRowStridedConv: Pass
Chisel.Dense.Sobel: Pass
Chisel.Dense.Sort_Merge: Pass
Chisel.Dense.Sort_Radix: Pass
Chisel.Dense.Stencil2D: Pass
Chisel.Dense.Stencil3D: Pass
Chisel.Dense.SW: Pass
Chisel.Dense.SYRK_col: Pass
Chisel.Dense.TPCHQ6: Pass
Chisel.Dense.TRSM: Pass
Chisel.Dense.Viterbi: Pass

Sparse

Chisel.Sparse.BFS_Bulk: Pass
Chisel.Sparse.BFS_Queue: Pass
Chisel.Sparse.GatherStore: Pass
Chisel.Sparse.PageRank_Bulk: Pass
Chisel.Sparse.PageRank: Pass
Chisel.Sparse.ScatterGather: Pass
Chisel.Sparse.SPMV_CRS: Pass
Chisel.Sparse.SPMV_ELL: Pass

Fixme

Chisel.Fixme.Backprop: Pass
Chisel.Fixme.SPMV_DumbPack: Fail [Execution]
↳  Cause: Execution timed out after 2000 seconds

Performance Results

Pass Comments:

Commits

Spatial commit

commit 53913e17392c6c7c50187fb04cc3033d0182c31a
Merge: 9cdbbe5 33d7fa0
Author: Matthew Feldman <[email protected]>
Date:   Wed Jan 31 10:50:10 2018 -0800

    Merge remote-tracking branch 'origin/pre-master'

commit 33d7fa012e6b90294951c5a3e6aa27e664bc2694
Merge: 06cfcab 3dd8159
Author: Matthew Feldman <[email protected]>
Date:   Wed Jan 31 10:48:20 2018 -0800

    Merge remote-tracking branch 'origin/develop' into retime

commit 3dd8159039f76ca7f7f678f4263800da731038d5
Merge: efad09d 55d92ed
Author: Matthew Feldman <[email protected]>
Date:   Wed Jan 31 10:48:11 2018 -0800

    Merge remote-tracking branch 'origin/fpga' into develop

commit efad09d11862469cccb6fbc73390f2231ba67067
Author: kelayamatoz <[email protected]>
Date:   Tue Jan 30 19:12:50 2018 -0800

    updated arria10 soc membase address

M	spatial/core/resources/cppgen/fringeArria10/Arria10AddressMap.h

Argon commit

commit dfdda6bd2d1e4a88e1ac26a52d1fc9ae3e9532c2
Merge: dd8ba76 578f2f6
Author: kelayamatoz <[email protected]>
Date:   Sat Jan 27 12:57:32 2018 -0800

    Merge branch 'develop' of https://github.com/stanford-ppl/argon into arria10

commit 578f2f6d0981f31e40d3e29fd5b6f8c4b5473025
Author: David Koeplinger <[email protected]>
Date:   Tue Jan 23 19:55:41 2018 -0800

    Fix CSE across unrelated type casts

M	core/src/argon/core/cake/LayerStaging.scala
M	core/src/argon/lang/FixPt.scala
M	core/src/argon/lang/FltPt.scala
M	core/src/argon/nodes/FixPt.scala
M	core/src/argon/nodes/FltPt.scala

commit ce91373df000c88b96f3cdaacd13825f02161683
Author: Matthew Feldman <[email protected]>
Date:   Mon Jan 22 19:52:20 2018 -0800

    add asic back in

M	core/src/argon/codegen/chiselgen/ChiselCodegen.scala

commit c1e6932c7f1dcc943f58a876402a3ba534f94f6e
Merge: f8911cb 27f3e3c
Author: Matthew Feldman <[email protected]>
Date:   Mon Jan 22 19:48:19 2018 -0800

    Merge remote-tracking branch 'origin/arria10' into fpga

Virtualized commit

commit 1a5adc8e9cd171f1a8c3f1f66dddbc04d89aa51f
Author: David Koeplinger <[email protected]>
Date:   Fri Jul 21 17:15:08 2017 -0700

    fix mistake in Structs

M	src/org/virtualized/Structs.scala

Spatial-Apps commit

commit 482cf7e8d89c3a9fac3de93eb698e0f1246a1ff0
Author: Matthew Feldman <[email protected]>
Date:   Tue Jan 30 15:55:41 2018 -0800

    multiplexed lb testing

M	src/UnitTests.scala

Test summary

Creation Time- 2018-01-31_10-50-16 | Status- debug | Type- chisel | tests- all | User- mattfel | Origin- london | Destination- tucson | Branch- master | Spatial- 53913 | Argon- dfdda | Virtualized- 1a5ad | Spatial-apps- 482cf

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