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Brnch:master Trgt:chisel
Matthew Feldman edited this page Jan 23, 2018
·
132 revisions
Time elapsed: 59 minutes, 59 seconds
Flags: --multifile=5 --synth
Chisel.Unit.ArbitraryLambda: Pass
Chisel.Unit.BasicCondFSM: Pass
Chisel.Unit.BasicFSM: Pass
Chisel.Unit.BlockReduce1D: Pass
Chisel.Unit.BlockReduce2D: Pass
Chisel.Unit.Breakpoint: Pass
Chisel.Unit.BubbledWriteTest: Pass
Chisel.Unit.ChangingCtrMax: Pass
Chisel.Unit.CompactingFifo: Pass
Chisel.Unit.CtrlEnable: Pass
Chisel.Unit.DeviceMemcpy: Pass
Chisel.Unit.DiagBanking: Pass
Chisel.Unit.DotProductFSM: Pass
Chisel.Unit.FifoLoadSRAMStore: Pass
Chisel.Unit.FifoLoadStore: Pass
Chisel.Unit.FifoPushPop: Pass
Chisel.Unit.FifoStackFSM: Pass
Chisel.Unit.FixPtInOutArg: Pass
Chisel.Unit.FixPtMem: Pass
Chisel.Unit.FloatBasics: Pass
Chisel.Unit.IndirectLoad: Pass
Chisel.Unit.InOutArg: Pass
Chisel.Unit.LaneMaskPar: Pass
Chisel.Unit.LUTTest: Pass
Chisel.Unit.MaskedWrite: Pass
Chisel.Unit.Memcpy2D: Pass
Chisel.Unit.MemTest1D: Pass
Chisel.Unit.MemTest2D: Pass
Chisel.Unit.MixedIOTest: Pass
Chisel.Unit.MultiplexedWriteTest: Pass
Chisel.Unit.MultiWriteBuffer: Pass
Chisel.Unit.Niter: Pass
Chisel.Unit.OHM: Pass
Chisel.Unit.PageBoundaryTest: Pass
Chisel.Unit.ParFifoLoad: Pass
Chisel.Unit.RetimedFifoBranch: Pass
Chisel.Unit.SequentialWrites: Pass
Chisel.Unit.SimpleFold: Pass
Chisel.Unit.SimpleMemReduce: Pass
Chisel.Unit.SimpleReduce: Pass
Chisel.Unit.SimpleSequential: Pass
Chisel.Unit.SimpleTileLoadStore: Pass
Chisel.Unit.SpecialMath: Pass
Chisel.Unit.SSV1D: Pass
Chisel.Unit.SSV2D: Pass
Chisel.Unit.StackLoadStore: Pass
Chisel.Unit.StridedLoad: Pass
Chisel.Unit.Tensor3D: Pass
Chisel.Unit.Tensor4D: Pass
Chisel.Unit.Tensor5D: Pass
Chisel.Unit.UnalignedFifoLoad: Pass
Chisel.Unit.UnalignedLd: Pass
Chisel.Unit.UniqueParallelLoad: Pass
Chisel.Dense.AES: Pass
Chisel.Dense.BasicBLAS: Pass
Chisel.Dense.BTC: Pass
Chisel.Dense.Convolution_FPGA: Pass
Chisel.Dense.Convolutions: Pass
Chisel.Dense.Differentiator: Pass
Chisel.Dense.DotProduct: Pass
Chisel.Dense.EdgeDetector: Pass
Chisel.Dense.FFT_Strided: Pass
Chisel.Dense.FFT_Transpose: Pass
Chisel.Dense.GDA: Pass
Chisel.Dense.GEMM_Blocked: Pass
Chisel.Dense.GEMM_NCubed: Pass
Chisel.Dense.Gibbs_Ising2D: Pass
Chisel.Dense.JPEG_Decompress: Pass
Chisel.Dense.JPEG_Markers: Pass
Chisel.Dense.Kmeans: Pass
Chisel.Dense.KMP: Pass
Chisel.Dense.MatMult_inner: Pass
Chisel.Dense.MatMult_outer: Pass
Chisel.Dense.MD_Grid: Pass
Chisel.Dense.MD_KNN: Pass
Chisel.Dense.NW: Pass
Chisel.Dense.OuterProduct: Pass
Chisel.Dense.SGD_minibatch: Pass
Chisel.Dense.SGD: Pass
Chisel.Dense.SHA1: Pass
Chisel.Dense.SimpleRowStridedConv: Pass
Chisel.Dense.Sobel: Pass
Chisel.Dense.Sort_Merge: Pass
Chisel.Dense.Sort_Radix: Pass
Chisel.Dense.Stencil2D: Pass
Chisel.Dense.Stencil3D: Pass
Chisel.Dense.SW: Pass
Chisel.Dense.SYRK_col: Pass
Chisel.Dense.TPCHQ6: Pass
Chisel.Dense.TRSM: Pass
Chisel.Dense.Viterbi: Pass
Chisel.Sparse.BFS_Bulk: Pass
Chisel.Sparse.BFS_Queue: Pass
Chisel.Sparse.GatherStore: Pass
Chisel.Sparse.PageRank_Bulk: Pass
Chisel.Sparse.PageRank: Pass
Chisel.Sparse.ScatterGather: Pass
Chisel.Sparse.SPMV_CRS: Pass
Chisel.Sparse.SPMV_ELL: Pass
Chisel.Fixme.Backprop: Pass
Chisel.Fixme.SPMV_DumbPack: Fail [Execution]
↳ Cause: Execution timed out after 2000 seconds
Spatial commit
commit 9b765d63843ec36741ac8e834619ce09e6f69848
Merge: bc8e9b1 592d263
Author: Matthew Feldman <[email protected]>
Date: Tue Jan 23 10:36:26 2018 -0800
Merge remote-tracking branch 'origin/fpga'
commit 592d26386d2d5b8c3376afe6c75bc5009723b840
Author: Matthew Feldman <[email protected]>
Date: Tue Jan 23 10:34:58 2018 -0800
tweak arria10 regression, zcu confirmed fixed
M apps
commit d129182e96dbe79d204b9269a13a0cecd46a2a81
Author: Matthew Feldman <[email protected]>
Date: Tue Jan 23 10:33:54 2018 -0800
tweak arria10 regression flow
M spatial/core/resources/chiselgen/app-level/scripts/scrape.sh
commit a11e61f9c4b6094ca011c2bb0baa2c7da2e7d2a2
Author: Matthew Feldman <[email protected]>
Date: Mon Jan 22 23:47:02 2018 -0800
fix too few debug regs for some apps and move zcu to cci axi ports
M spatial/core/resources/chiselgen/app-level/Top.scala
M spatial/core/resources/chiselgen/template-level/fringeHW/MAGCore.scala
M spatial/core/resources/chiselgen/template-level/fringeHW/MAGToAXI4Bridge.scala
M spatial/core/resources/chiselgen/template-level/fringeZynq/build/bdproject.tcl
M spatial/core/resources/chiselgen/template-level/fringeZynq/build/vivado.tcl
commit e8e5faa4d27a5d557a3a60c61f914e01cbd210a8
Author: Matthew Feldman <[email protected]>
Date: Mon Jan 22 20:12:39 2018 -0800
merge of arria10
D .ee109_old/Computer_System_tb.v
D .ee109_old/Intro2Linux/README.md
D .ee109_old/Intro2Linux/increment_leds/Makefile
D .ee109_old/Intro2Linux/increment_leds/address_map_arm.h
D .ee109_old/Intro2Linux/increment_leds/led.c
D .ee109_old/Intro2Linux/pushbutton_irq_handler/Makefile
D .ee109_old/Intro2Linux/pushbutton_irq_handler/README
D .ee109_old/Intro2Linux/pushbutton_irq_handler/pushbutton_irq_handler.c
D .ee109_old/Intro2Spatial/README.md
D .ee109_old/Top_tb.v
D .ee109_old/VideoSysSim/fringeDE1SoC/.qsys_edit/Computer_System.xml
D .ee109_old/VideoSysSim/fringeDE1SoC/.qsys_edit/Computer_System_schematic.nlv
D .ee109_old/VideoSysSim/fringeDE1SoC/.qsys_edit/Video_In_Subsystem_schematic.nlv
D .ee109_old/VideoSysSim/fringeDE1SoC/.qsys_edit/filters.xml
D .ee109_old/VideoSysSim/fringeDE1SoC/.qsys_edit/preferences.xml
D .ee109_old/VideoSysSim/fringeDE1SoC/VGA_Subsystem.qsys
D .ee109_old/VideoSysSim/fringeDE1SoC/Video_In_Subsystem.qsys
D .ee109_old/VideoSysSim/fringeDE1SoC/Video_In_Subsystem/Computer_System.bsf
D .ee109_old/VideoSysSim/fringeDE1SoC/Video_In_Subsystem/Computer_System.cmp
D .ee109_old/VideoSysSim/fringeDE1SoC/Video_In_Subsystem/Computer_System_bb.v
D .ee109_old/VideoSysSim/fringeDE1SoC/Video_In_Subsystem/Computer_System_inst.v
D .ee109_old/VideoSysSim/fringeDE1SoC/Video_In_Subsystem/Computer_System_inst.vhd
D .ee109_old/VideoSysSim/fringeDE1SoC/simulation/Top.v
D .ee109_old/VideoSysSim/fringeDE1SoC/simulation/Top_tb.v
D .ee109_old/VideoSysSim/fringeDE1SoC/simulation/a.out
D .ee109_old/VideoSysSim/fringeDE1SoC/simulation/gtk_template.gtkw
D .ee109_old/VideoSysSim/fringeDE1SoC/simulation/simulate.sh
D .ee109_old/VideoSysSim/fringeDE1SoC/simulation/test.vcd
D .ee109_old/VideoSysSim/fringeDE1SoC/simulation/topSim.cr.mti
D .ee109_old/VideoSysSim/fringeDE1SoC/simulation/topSim.mpf
D .ee109_old/VideoSysSim/fringeDE1SoC/simulation/topTest
D .ee109_old/VideoSysSim/fringeDE1SoC/simulation/work/_info
D .ee109_old/VideoSysSim/fringeDE1SoC/simulation/work/_lib.qdb
D .ee109_old/VideoSysSim/fringeDE1SoC/simulation/work/_lib1_4.qdb
D .ee109_old/VideoSysSim/fringeDE1SoC/simulation/work/_lib1_4.qpg
D .ee109_old/VideoSysSim/fringeDE1SoC/simulation/work/_lib1_4.qtl
D .ee109_old/VideoSysSim/fringeDE1SoC/simulation/work/_vmake
D .ee109_old/moduleSims/Computer_System_Expansion_JP1.v
D .ee109_old/moduleSims/Computer_System_Expansion_JP1_tb.v
D .ee109_old/moduleSims/JP1Test
D .ee109_old/moduleSims/Top.v
D .ee109_old/moduleSims/a.out
D .ee109_old/moduleSims/gtk_template.gtkw
D .ee109_old/moduleSims/simulate.sh
D .ee109_old/moduleSims/test.vcd
D .ee109_old/newCppAPIChanges/Makefile
D .ee109_old/newCppAPIChanges/Top
D .ee109_old/newCppAPIChanges/TopHost.cpp
D .ee109_old/newCppAPIChanges/cpptypes.h
D .ee109_old/newCppAPIChanges/datastructures/cppDeliteArraybool.h
D .ee109_old/newCppAPIChanges/datastructures/cppDeliteArraycppDeliteArrayint32_t.h
D .ee109_old/newCppAPIChanges/datastructures/cppDeliteArraydouble.h
D .ee109_old/newCppAPIChanges/datastructures/cppDeliteArrayint32_t.h
D .ee109_old/newCppAPIChanges/datastructures/cppDeliteArrays.h
D .ee109_old/newCppAPIChanges/datastructures/cppDeliteArraystring.h
D .ee109_old/newCppAPIChanges/datastructures/cppDeliteStructs.h
D .ee109_old/newCppAPIChanges/datastructures/cppDeliteVariables.h
D .ee109_old/newCppAPIChanges/datastructures/cppRefbool.h
D .ee109_old/newCppAPIChanges/datastructures/cppRefcppDeliteArraybool.h
D .ee109_old/newCppAPIChanges/datastructures/cppRefcppDeliteArraycppDeliteArrayint32_t.h
D .ee109_old/newCppAPIChanges/datastructures/cppRefcppDeliteArraydouble.h
D .ee109_old/newCppAPIChanges/datastructures/cppRefcppDeliteArrayint32_t.h
D .ee109_old/newCppAPIChanges/datastructures/cppRefcppDeliteArraystring.h
D .ee109_old/newCppAPIChanges/datastructures/cppRefint32_t.h
D .ee109_old/newCppAPIChanges/datastructures/cppRefstring.h
D .ee109_old/newCppAPIChanges/datastructures/cpptypes.h
D .ee109_old/newCppAPIChanges/datastructures/static/Config.cpp
D .ee109_old/newCppAPIChanges/datastructures/static/Config.h
D .ee109_old/newCppAPIChanges/datastructures/static/DeliteCpp.cpp
D .ee109_old/newCppAPIChanges/datastructures/static/DeliteCpp.h
D .ee109_old/newCppAPIChanges/datastructures/static/DeliteCppProfiler.cpp
D .ee109_old/newCppAPIChanges/datastructures/static/DeliteCppProfiler.h
D .ee109_old/newCppAPIChanges/datastructures/static/DeliteCppRandom.h
D .ee109_old/newCppAPIChanges/datastructures/static/DeliteDatastructures.h
D .ee109_old/newCppAPIChanges/datastructures/static/DeliteFileInputStream.h
D .ee109_old/newCppAPIChanges/datastructures/static/DeliteFileOutputStream.h
D .ee109_old/newCppAPIChanges/datastructures/static/DeliteFileSystem.h
D .ee109_old/newCppAPIChanges/datastructures/static/DeliteMemory.cpp
D .ee109_old/newCppAPIChanges/datastructures/static/DeliteMemory.h
D .ee109_old/newCppAPIChanges/datastructures/static/DeliteNamespaces.h
D .ee109_old/newCppAPIChanges/datastructures/static/DeliteString.h
D .ee109_old/newCppAPIChanges/datastructures/static/DeliteThreadPool.cpp
D .ee109_old/newCppAPIChanges/datastructures/static/MultiLoopSync.h
D .ee109_old/newCppAPIChanges/datastructures/static/PrettyPrintMacros.h
D .ee109_old/newCppAPIChanges/datastructures/static/cppDeliteArray.cpp
D .ee109_old/newCppAPIChanges/datastructures/static/cppHashMap.h
D .ee109_old/newCppAPIChanges/datastructures/static/cppInit.cpp
D .ee109_old/newCppAPIChanges/datastructures/static/cppInit.h
D .ee109_old/newCppAPIChanges/datastructures/static/cppList.cpp
D .ee109_old/newCppAPIChanges/datastructures/static/cppList.h
D .ee109_old/newCppAPIChanges/datastructures/static/cppRef.cpp
D .ee109_old/newCppAPIChanges/datastructures/static/cppRef.h
D .ee109_old/newCppAPIChanges/datastructures/static/pcmHelper.cpp
D .ee109_old/newCppAPIChanges/datastructures/static/pcmHelper.h
D .ee109_old/newCppAPIChanges/datastructures/static/standalone/DeliteStandaloneMain.cpp
D .ee109_old/newCppAPIChanges/datastructures/static/standalone/DeliteStandaloneMain.h
D .ee109_old/newCppAPIChanges/datastructures/static/standalone/Makefile.standalone
D .ee109_old/newCppAPIChanges/files_listfringeSW/Callbacks.h
D .ee109_old/newCppAPIChanges/files_listfringeSW/DUT.h
D .ee109_old/newCppAPIChanges/files_listfringeSW/DUT.mk
D .ee109_old/newCppAPIChanges/files_listfringeSW/DUTTester.h
D .ee109_old/newCppAPIChanges/files_listfringeSW/FringeContext.h
D .ee109_old/newCppAPIChanges/files_listfringeSW/FringeContextBase.h
D .ee109_old/newCppAPIChanges/files_listfringeSW/FringeContextSim.h
D .ee109_old/newCppAPIChanges/files_listfringeSW/PeekPokeTester.h
D .ee109_old/newCppAPIChanges/fringeDE1SoC/DE1SoC.h
D .ee109_old/newCppAPIChanges/fringeDE1SoC/DE1SoCAddressMap.h
D .ee109_old/newCppAPIChanges/fringeDE1SoC/FringeContext.h
D .ee109_old/newCppAPIChanges/fringeDE1SoC/FringeContextBase.h
D .ee109_old/newCppAPIChanges/fringeDE1SoC/FringeContextDE1SoC.h
D .ee109_old/newCppAPIChanges/fringeDE1SoC/FringeContextZynq
D .ee109_old/newCppAPIChanges/fringeDE1SoC/Makefile
D .ee109_old/newCppAPIChanges/fringeDE1SoC/ZynqAddressMap
D .ee109_old/newCppAPIChanges/fringeDE1SoC/ZynqUtils.cpp
D .ee109_old/newCppAPIChanges/fringeDE1SoC/ZynqUtils.h
D .ee109_old/newCppAPIChanges/fringeDE1SoC/utils/run.sh
D .ee109_old/newCppAPIChanges/fringeDE1SoC/utils/set_perms
D .ee109_old/newCppAPIChanges/fringeVCS/FringeContext.h
D .ee109_old/newCppAPIChanges/fringeVCS/FringeContextBase.h
D .ee109_old/newCppAPIChanges/fringeVCS/FringeContextVCS.h
D .ee109_old/newCppAPIChanges/fringeVCS/channel.h
D .ee109_old/newCppAPIChanges/fringeVCS/commonDefs.h
D .ee109_old/newCppAPIChanges/fringeVCS/simDefs.h
D .ee109_old/newCppAPIChanges/fringeZynq/FringeContext.h
D .ee109_old/newCppAPIChanges/fringeZynq/FringeContextBase.h
D .ee109_old/newCppAPIChanges/fringeZynq/Makefile
D .ee109_old/newCppAPIChanges/fringeZynq/ZynqAddressMap.h
D .ee109_old/newCppAPIChanges/fringeZynq/ZynqUtils.cpp
D .ee109_old/newCppAPIChanges/fringeZynq/ZynqUtils.h
D .ee109_old/newCppAPIChanges/fringeZynq/utils/run.sh
D .ee109_old/newCppAPIChanges/fringeZynq/utils/set_perms
D .ee109_old/newCppAPIChanges/functions.cpp
D .ee109_old/newCppAPIChanges/functions.h
M .gitignore
M apps
M argon
A bin/arria10_debuggers/FringeContextArria10.h
A bin/arria10_debuggers/FringeContextZynq.h
A bin/arria10_debuggers/ZynqAddressMap.h
A bin/arria10_debuggers/clean.c
A bin/arria10_debuggers/crosscomp
A bin/arria10_debuggers/generated_debugRegs.h
A bin/arria10_debuggers/get_page_size.c
A bin/arria10_debuggers/hello-world.c
A bin/arria10_debuggers/read_c0000000.c
A bin/arria10_debuggers/read_sdram_hps.c
A bin/arria10_debuggers/read_sram.c
A bin/arria10_debuggers/read_sysid.c
A bin/arria10_debuggers/regen_cpp.sh
A bin/arria10_debuggers/run_app.c
A bin/arria10_debuggers/run_inoutarg.c
A bin/arria10_debuggers/set_sdram_hps.c
A bin/arria10_debuggers/test_arria10.sh
A bin/arria10_debuggers/testbenches/Arria10_tb.v
A bin/arria10_debuggers/testbenches/RetimeShiftRegister.sv
A bin/arria10_debuggers/testbenches/RetimeShiftRegister.v
A bin/arria10_debuggers/testbenches/SRAMVerilogAWS.v
A bin/arria10_debuggers/testbenches/Top_DUT.v
A bin/arria10_debuggers/testbenches/arria10Test
A bin/arria10_debuggers/testbenches/arria10_argInOuts.vcd
A bin/arria10_debuggers/testbenches/dramwritetest.gtkw
A bin/arria10_debuggers/testbenches/simulate.sh
M bin/update_resources.sh
D spatial/core/resources/chiselgen/altera-goodies/AlteraBundles.scala
D spatial/core/resources/chiselgen/altera-goodies/StreamPixBuffer2ARM.scala
D spatial/core/resources/chiselgen/altera-goodies/address_map_arm.h
D spatial/core/resources/chiselgen/altera-goodies/altera_up_avalon_video_decoder/altera_up_avalon_video_decoder_hw.tcl
D spatial/core/resources/chiselgen/altera-goodies/altera_up_avalon_video_decoder/hdl/altera_up_avalon_video_decoder.v
D spatial/core/resources/chiselgen/altera-goodies/altera_up_avalon_video_decoder/hdl/altera_up_video_camera_decoder.v
D spatial/core/resources/chiselgen/altera-goodies/altera_up_avalon_video_decoder/hdl/altera_up_video_camera_decoder_RGB.v
D spatial/core/resources/chiselgen/altera-goodies/altera_up_avalon_video_decoder/hdl/altera_up_video_camera_decoder_bayer.v
D spatial/core/resources/chiselgen/altera-goodies/altera_up_avalon_video_decoder/hdl/altera_up_video_decoder_add_endofpacket.v
D spatial/core/resources/chiselgen/altera-goodies/altera_up_avalon_video_decoder/hdl/altera_up_video_dual_clock_fifo.v
D spatial/core/resources/chiselgen/altera-goodies/altera_up_avalon_video_decoder/hdl/altera_up_video_itu_656_decoder.v
D spatial/core/resources/chiselgen/altera-goodies/altera_up_avalon_video_dma_controller/HAL/inc/altera_up_avalon_video_dma_controller.h
D spatial/core/resources/chiselgen/altera-goodies/altera_up_avalon_video_dma_controller/HAL/src/altera_up_avalon_video_dma_controller.c
D spatial/core/resources/chiselgen/altera-goodies/altera_up_avalon_video_dma_controller/altera_up_avalon_video_dma_controller_hw.tcl
D spatial/core/resources/chiselgen/altera-goodies/altera_up_avalon_video_dma_controller/hdl/altera_up_avalon_video_dma_controller.v
D spatial/core/resources/chiselgen/altera-goodies/altera_up_avalon_video_dma_controller/hdl/altera_up_video_dma_control_slave.v
D spatial/core/resources/chiselgen/altera-goodies/altera_up_avalon_video_dma_controller/hdl/altera_up_video_dma_to_memory.v
D spatial/core/resources/chiselgen/altera-goodies/altera_up_avalon_video_dma_controller/hdl/altera_up_video_dma_to_stream.v
D spatial/core/resources/chiselgen/altera-goodies/altera_up_avalon_video_dma_ctrl_addr_trans/altera_up_avalon_video_dma_ctrl_addr_trans.v
D spatial/core/resources/chiselgen/altera-goodies/altera_up_avalon_video_dma_ctrl_addr_trans/altera_up_avalon_video_dma_ctrl_addr_trans_hw.tcl
D spatial/core/resources/chiselgen/altera-goodies/altera_up_avalon_video_vga_controller/altera_up_avalon_video_vga_controller_hw.tcl
D spatial/core/resources/chiselgen/altera-goodies/altera_up_avalon_video_vga_controller/hdl/altera_up_avalon_video_vga_controller.v
D spatial/core/resources/chiselgen/altera-goodies/altera_up_avalon_video_vga_controller/hdl/altera_up_avalon_video_vga_timing.v
D spatial/core/resources/chiselgen/altera-goodies/interfaces.v
M spatial/core/resources/chiselgen/app-level/Makefile
M spatial/core/resources/chiselgen/app-level/Top.scala
A spatial/core/resources/chiselgen/app-level/scripts/arria10.mk
A spatial/core/resources/chiselgen/template-level/fringeArria10/FringeArria10.scala
A spatial/core/resources/chiselgen/template-level/fringeArria10/RetimeShiftRegister.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/SRAMVerilogAWS.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/bigIP/BigIPArria10.scala
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/.pr_region_alternate_bak/.synth_bak/pr_region_alternate.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/.pr_region_alternate_bak/altera_avalon_sc_fifo_171/synth/altera_avalon_sc_fifo.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/.pr_region_alternate_bak/altera_avalon_st_adapter_171/synth/pr_region_alternate_altera_avalon_st_adapter_171_yxzsrmq.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/.pr_region_alternate_bak/altera_merlin_demultiplexer_171/synth/pr_region_alternate_altera_merlin_demultiplexer_171_qxprg2y.sv
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/.pr_region_alternate_bak/altera_merlin_demultiplexer_171/synth/pr_region_alternate_altera_merlin_demultiplexer_171_t7zxpci.sv
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/.pr_region_alternate_bak/altera_merlin_master_agent_171/synth/altera_merlin_master_agent.sv
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/.pr_region_alternate_bak/altera_merlin_master_translator_171/synth/altera_merlin_master_translator.sv
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/.pr_region_alternate_bak/altera_merlin_multiplexer_171/synth/altera_merlin_arbitrator.sv
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/.pr_region_alternate_bak/altera_merlin_multiplexer_171/synth/pr_region_alternate_altera_merlin_multiplexer_171_7tds3oi.sv
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/.pr_region_alternate_bak/altera_merlin_multiplexer_171/synth/pr_region_alternate_altera_merlin_multiplexer_171_bwlg3ma.sv
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/.pr_region_alternate_bak/altera_merlin_router_171/synth/pr_region_alternate_altera_merlin_router_171_dz476wq.sv
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/.pr_region_alternate_bak/altera_merlin_router_171/synth/pr_region_alternate_altera_merlin_router_171_tzwfaga.sv
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A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_axi_bridge_0/synth/ghrd_10as066n2_axi_bridge_0.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_button_pio.ip
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_button_pio/altera_avalon_pio_171/synth/ghrd_10as066n2_button_pio_altera_avalon_pio_171_3t26uui.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_button_pio/ghrd_10as066n2_button_pio.bsf
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_button_pio/ghrd_10as066n2_button_pio.cmp
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_button_pio/ghrd_10as066n2_button_pio.html
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_button_pio/ghrd_10as066n2_button_pio.qgsynthc
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_button_pio/ghrd_10as066n2_button_pio.qip
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_button_pio/ghrd_10as066n2_button_pio.regmap
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_button_pio/ghrd_10as066n2_button_pio.sopcinfo
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_button_pio/ghrd_10as066n2_button_pio.xml
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_button_pio/ghrd_10as066n2_button_pio_bb.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_button_pio/ghrd_10as066n2_button_pio_generation.rpt
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_button_pio/ghrd_10as066n2_button_pio_generation_previous.rpt
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_button_pio/ghrd_10as066n2_button_pio_inst.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_button_pio/ghrd_10as066n2_button_pio_inst.vhd
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_button_pio/synth/ghrd_10as066n2_button_pio.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_clk_0.ip
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_clk_0/ghrd_10as066n2_clk_0.bsf
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_clk_0/ghrd_10as066n2_clk_0.cmp
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_clk_0/ghrd_10as066n2_clk_0.html
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_clk_0/ghrd_10as066n2_clk_0.qgsynthc
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_clk_0/ghrd_10as066n2_clk_0.qip
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_clk_0/ghrd_10as066n2_clk_0.sopcinfo
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_clk_0/ghrd_10as066n2_clk_0.xml
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_clk_0/ghrd_10as066n2_clk_0_bb.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_clk_0/ghrd_10as066n2_clk_0_generation.rpt
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_clk_0/ghrd_10as066n2_clk_0_generation_previous.rpt
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_clk_0/ghrd_10as066n2_clk_0_inst.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_clk_0/ghrd_10as066n2_clk_0_inst.vhd
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_clk_0/synth/ghrd_10as066n2_clk_0.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_conduit_bridge_0/ghrd_10as066n2_conduit_bridge_0_generation.rpt
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_dipsw_pio.ip
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_dipsw_pio/altera_avalon_pio_171/synth/ghrd_10as066n2_dipsw_pio_altera_avalon_pio_171_67u3hiq.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_dipsw_pio/ghrd_10as066n2_dipsw_pio.bsf
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_dipsw_pio/ghrd_10as066n2_dipsw_pio.cmp
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_dipsw_pio/ghrd_10as066n2_dipsw_pio.html
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_dipsw_pio/ghrd_10as066n2_dipsw_pio.qgsynthc
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_dipsw_pio/ghrd_10as066n2_dipsw_pio.qip
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_dipsw_pio/ghrd_10as066n2_dipsw_pio.regmap
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_dipsw_pio/ghrd_10as066n2_dipsw_pio.sopcinfo
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_dipsw_pio/ghrd_10as066n2_dipsw_pio.xml
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_dipsw_pio/ghrd_10as066n2_dipsw_pio_bb.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_dipsw_pio/ghrd_10as066n2_dipsw_pio_generation.rpt
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_dipsw_pio/ghrd_10as066n2_dipsw_pio_generation_previous.rpt
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_dipsw_pio/ghrd_10as066n2_dipsw_pio_inst.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_dipsw_pio/ghrd_10as066n2_dipsw_pio_inst.vhd
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_dipsw_pio/synth/ghrd_10as066n2_dipsw_pio.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_emif_hps.ip
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_emif_hps/altera_emif_a10_hps_171/synth/ghrd_10as066n2_emif_hps_altera_emif_a10_hps_171_or5co3i.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_emif_hps/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_abphy_mux.sv
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_emif_hps/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_afi_if.sv
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_emif_hps/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_buf_bdir_df.sv
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_emif_hps/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_buf_bdir_se.sv
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_emif_hps/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_buf_udir_cp_i.sv
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_emif_hps/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_buf_udir_df_i.sv
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_emif_hps/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_buf_udir_df_o.sv
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_emif_hps/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_buf_udir_se_i.sv
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_emif_hps/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_buf_udir_se_o.sv
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_emif_hps/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_buf_unused.sv
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_emif_hps/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_bufs.sv
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_emif_hps/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_cal_counter.sv
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_emif_hps/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_core_clks_rsts.sv
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_emif_hps/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_hmc_amm_data_if.sv
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_emif_hps/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_hmc_ast_data_if.sv
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_emif_hps/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_hmc_avl_if.sv
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_emif_hps/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_hmc_mmr_if.sv
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_emif_hps/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_hmc_sideband_if.sv
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_emif_hps/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_hps_clks_rsts.sv
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_emif_hps/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_io_tiles.sv
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_emif_hps/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_io_tiles_abphy.sv
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_emif_hps/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_io_tiles_wrap.sv
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_emif_hps/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_oct.sv
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_emif_hps/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_pll.sv
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_emif_hps/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_pll_extra_clks.sv
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_emif_hps/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_pll_fast_sim.sv
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_emif_hps/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_regs.sv
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_emif_hps/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_seq_if.sv
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_emif_hps/altera_emif_arch_nf_171/synth/altera_oct.sv
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_emif_hps/altera_emif_arch_nf_171/synth/altera_oct_um_fsm.sv
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_emif_hps/altera_emif_arch_nf_171/synth/altera_std_synchronizer_nocut.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_emif_hps/altera_emif_arch_nf_171/synth/emif.pre.xml
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_emif_hps/altera_emif_arch_nf_171/synth/ghrd_10as066n2_emif_hps_altera_emif_arch_nf_171_qhcayby.sdc
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_emif_hps/altera_emif_arch_nf_171/synth/ghrd_10as066n2_emif_hps_altera_emif_arch_nf_171_qhcayby.sv
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_emif_hps/altera_emif_arch_nf_171/synth/ghrd_10as066n2_emif_hps_altera_emif_arch_nf_171_qhcayby_io_aux.sv
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_emif_hps/altera_emif_arch_nf_171/synth/ghrd_10as066n2_emif_hps_altera_emif_arch_nf_171_qhcayby_ip_parameters.tcl
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_emif_hps/altera_emif_arch_nf_171/synth/ghrd_10as066n2_emif_hps_altera_emif_arch_nf_171_qhcayby_parameters.tcl
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_emif_hps/altera_emif_arch_nf_171/synth/ghrd_10as066n2_emif_hps_altera_emif_arch_nf_171_qhcayby_pin_map.tcl
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_emif_hps/altera_emif_arch_nf_171/synth/ghrd_10as066n2_emif_hps_altera_emif_arch_nf_171_qhcayby_readme.txt
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_emif_hps/altera_emif_arch_nf_171/synth/ghrd_10as066n2_emif_hps_altera_emif_arch_nf_171_qhcayby_report_io_timing.tcl
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_emif_hps/altera_emif_arch_nf_171/synth/ghrd_10as066n2_emif_hps_altera_emif_arch_nf_171_qhcayby_report_timing.tcl
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_emif_hps/altera_emif_arch_nf_171/synth/ghrd_10as066n2_emif_hps_altera_emif_arch_nf_171_qhcayby_report_timing_core.tcl
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_emif_hps/altera_emif_arch_nf_171/synth/ghrd_10as066n2_emif_hps_altera_emif_arch_nf_171_qhcayby_seq_cal.hex
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_emif_hps/altera_emif_arch_nf_171/synth/ghrd_10as066n2_emif_hps_altera_emif_arch_nf_171_qhcayby_seq_params_sim.hex
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_emif_hps/altera_emif_arch_nf_171/synth/ghrd_10as066n2_emif_hps_altera_emif_arch_nf_171_qhcayby_seq_params_sim.txt
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_emif_hps/altera_emif_arch_nf_171/synth/ghrd_10as066n2_emif_hps_altera_emif_arch_nf_171_qhcayby_seq_params_synth.hex
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_emif_hps/altera_emif_arch_nf_171/synth/ghrd_10as066n2_emif_hps_altera_emif_arch_nf_171_qhcayby_seq_params_synth.txt
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_emif_hps/altera_emif_arch_nf_171/synth/ghrd_10as066n2_emif_hps_altera_emif_arch_nf_171_qhcayby_top.sv
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_emif_hps/altera_emif_arch_nf_171/synth/ghrd_10as066n2_emif_hps_altera_emif_arch_nf_171_qhcayby_utils.tcl
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_emif_hps/altera_emif_arch_nf_171/synth/twentynm_io_12_lane_abphy.sv
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_emif_hps/altera_emif_arch_nf_171/synth/twentynm_io_12_lane_encrypted_abphy.sv
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_emif_hps/altera_emif_arch_nf_171/synth/twentynm_io_12_lane_nf5es_encrypted_abphy.sv
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_emif_hps/ghrd_10as066n2_emif_hps.bsf
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_emif_hps/ghrd_10as066n2_emif_hps.cmp
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_emif_hps/ghrd_10as066n2_emif_hps.html
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_emif_hps/ghrd_10as066n2_emif_hps.qgsynthc
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_emif_hps/ghrd_10as066n2_emif_hps.qip
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_emif_hps/ghrd_10as066n2_emif_hps.sopcinfo
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_emif_hps/ghrd_10as066n2_emif_hps.xml
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_emif_hps/ghrd_10as066n2_emif_hps_bb.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_emif_hps/ghrd_10as066n2_emif_hps_generation.rpt
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_emif_hps/ghrd_10as066n2_emif_hps_generation_previous.rpt
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_emif_hps/ghrd_10as066n2_emif_hps_inst.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_emif_hps/ghrd_10as066n2_emif_hps_inst.vhd
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_emif_hps/synth/ghrd_10as066n2_emif_hps.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram0_m.ip
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram0_m/altera_avalon_packets_to_master_171/synth/altera_avalon_packets_to_master.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram0_m/altera_avalon_sc_fifo_171/synth/altera_avalon_sc_fifo.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram0_m/altera_avalon_st_bytes_to_packets_171/synth/altera_avalon_st_bytes_to_packets.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram0_m/altera_avalon_st_packets_to_bytes_171/synth/altera_avalon_st_packets_to_bytes.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram0_m/altera_jtag_avalon_master_171/synth/ghrd_10as066n2_f2sdram0_m_altera_jtag_avalon_master_171_wqhllki.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram0_m/altera_jtag_dc_streaming_171/synth/altera_avalon_st_clock_crosser.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram0_m/altera_jtag_dc_streaming_171/synth/altera_avalon_st_idle_inserter.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram0_m/altera_jtag_dc_streaming_171/synth/altera_avalon_st_idle_remover.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram0_m/altera_jtag_dc_streaming_171/synth/altera_avalon_st_jtag_interface.sdc
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram0_m/altera_jtag_dc_streaming_171/synth/altera_avalon_st_jtag_interface.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram0_m/altera_jtag_dc_streaming_171/synth/altera_avalon_st_pipeline_base.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram0_m/altera_jtag_dc_streaming_171/synth/altera_avalon_st_pipeline_stage.sv
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram0_m/altera_jtag_dc_streaming_171/synth/altera_jtag_dc_streaming.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram0_m/altera_jtag_dc_streaming_171/synth/altera_jtag_sld_node.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram0_m/altera_jtag_dc_streaming_171/synth/altera_jtag_streaming.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram0_m/altera_jtag_dc_streaming_171/synth/altera_std_synchronizer_nocut.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram0_m/altera_reset_controller_171/synth/altera_reset_controller.sdc
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram0_m/altera_reset_controller_171/synth/altera_reset_controller.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram0_m/altera_reset_controller_171/synth/altera_reset_synchronizer.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram0_m/channel_adapter_171/synth/ghrd_10as066n2_f2sdram0_m_channel_adapter_171_2swajja.sv
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram0_m/channel_adapter_171/synth/ghrd_10as066n2_f2sdram0_m_channel_adapter_171_vh2yu6y.sv
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram0_m/ghrd_10as066n2_f2sdram0_m.bsf
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram0_m/ghrd_10as066n2_f2sdram0_m.cmp
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram0_m/ghrd_10as066n2_f2sdram0_m.html
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram0_m/ghrd_10as066n2_f2sdram0_m.qgsynthc
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram0_m/ghrd_10as066n2_f2sdram0_m.qip
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram0_m/ghrd_10as066n2_f2sdram0_m.sopcinfo
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram0_m/ghrd_10as066n2_f2sdram0_m.xml
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram0_m/ghrd_10as066n2_f2sdram0_m_bb.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram0_m/ghrd_10as066n2_f2sdram0_m_generation.rpt
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram0_m/ghrd_10as066n2_f2sdram0_m_generation_previous.rpt
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram0_m/ghrd_10as066n2_f2sdram0_m_inst.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram0_m/ghrd_10as066n2_f2sdram0_m_inst.vhd
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram0_m/synth/ghrd_10as066n2_f2sdram0_m.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram0_m/timing_adapter_171/synth/ghrd_10as066n2_f2sdram0_m_timing_adapter_171_xf5weri.sv
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram2_m.ip
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram2_m/altera_avalon_packets_to_master_171/synth/altera_avalon_packets_to_master.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram2_m/altera_avalon_sc_fifo_171/synth/altera_avalon_sc_fifo.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram2_m/altera_avalon_st_bytes_to_packets_171/synth/altera_avalon_st_bytes_to_packets.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram2_m/altera_avalon_st_packets_to_bytes_171/synth/altera_avalon_st_packets_to_bytes.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram2_m/altera_jtag_avalon_master_171/synth/ghrd_10as066n2_f2sdram2_m_altera_jtag_avalon_master_171_wqhllki.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram2_m/altera_jtag_dc_streaming_171/synth/altera_avalon_st_clock_crosser.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram2_m/altera_jtag_dc_streaming_171/synth/altera_avalon_st_idle_inserter.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram2_m/altera_jtag_dc_streaming_171/synth/altera_avalon_st_idle_remover.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram2_m/altera_jtag_dc_streaming_171/synth/altera_avalon_st_jtag_interface.sdc
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram2_m/altera_jtag_dc_streaming_171/synth/altera_avalon_st_jtag_interface.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram2_m/altera_jtag_dc_streaming_171/synth/altera_avalon_st_pipeline_base.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram2_m/altera_jtag_dc_streaming_171/synth/altera_avalon_st_pipeline_stage.sv
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram2_m/altera_jtag_dc_streaming_171/synth/altera_jtag_dc_streaming.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram2_m/altera_jtag_dc_streaming_171/synth/altera_jtag_sld_node.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram2_m/altera_jtag_dc_streaming_171/synth/altera_jtag_streaming.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram2_m/altera_jtag_dc_streaming_171/synth/altera_std_synchronizer_nocut.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram2_m/altera_reset_controller_171/synth/altera_reset_controller.sdc
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram2_m/altera_reset_controller_171/synth/altera_reset_controller.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram2_m/altera_reset_controller_171/synth/altera_reset_synchronizer.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram2_m/channel_adapter_171/synth/ghrd_10as066n2_f2sdram2_m_channel_adapter_171_2swajja.sv
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram2_m/channel_adapter_171/synth/ghrd_10as066n2_f2sdram2_m_channel_adapter_171_vh2yu6y.sv
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram2_m/ghrd_10as066n2_f2sdram2_m.bsf
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram2_m/ghrd_10as066n2_f2sdram2_m.cmp
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram2_m/ghrd_10as066n2_f2sdram2_m.html
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram2_m/ghrd_10as066n2_f2sdram2_m.qgsynthc
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram2_m/ghrd_10as066n2_f2sdram2_m.qip
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram2_m/ghrd_10as066n2_f2sdram2_m.sopcinfo
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram2_m/ghrd_10as066n2_f2sdram2_m.xml
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram2_m/ghrd_10as066n2_f2sdram2_m_bb.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram2_m/ghrd_10as066n2_f2sdram2_m_generation.rpt
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram2_m/ghrd_10as066n2_f2sdram2_m_generation_previous.rpt
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram2_m/ghrd_10as066n2_f2sdram2_m_inst.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram2_m/ghrd_10as066n2_f2sdram2_m_inst.vhd
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram2_m/synth/ghrd_10as066n2_f2sdram2_m.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram2_m/timing_adapter_171/synth/ghrd_10as066n2_f2sdram2_m_timing_adapter_171_xf5weri.sv
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_fpga_m.ip
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_fpga_m/altera_avalon_packets_to_master_171/synth/altera_avalon_packets_to_master.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_fpga_m/altera_avalon_sc_fifo_171/synth/altera_avalon_sc_fifo.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_fpga_m/altera_avalon_st_bytes_to_packets_171/synth/altera_avalon_st_bytes_to_packets.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_fpga_m/altera_avalon_st_packets_to_bytes_171/synth/altera_avalon_st_packets_to_bytes.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_fpga_m/altera_jtag_avalon_master_171/synth/ghrd_10as066n2_fpga_m_altera_jtag_avalon_master_171_wqhllki.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_fpga_m/altera_jtag_dc_streaming_171/synth/altera_avalon_st_clock_crosser.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_fpga_m/altera_jtag_dc_streaming_171/synth/altera_avalon_st_idle_inserter.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_fpga_m/altera_jtag_dc_streaming_171/synth/altera_avalon_st_idle_remover.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_fpga_m/altera_jtag_dc_streaming_171/synth/altera_avalon_st_jtag_interface.sdc
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_fpga_m/altera_jtag_dc_streaming_171/synth/altera_avalon_st_jtag_interface.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_fpga_m/altera_jtag_dc_streaming_171/synth/altera_avalon_st_pipeline_base.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_fpga_m/altera_jtag_dc_streaming_171/synth/altera_avalon_st_pipeline_stage.sv
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_fpga_m/altera_jtag_dc_streaming_171/synth/altera_jtag_dc_streaming.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_fpga_m/altera_jtag_dc_streaming_171/synth/altera_jtag_sld_node.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_fpga_m/altera_jtag_dc_streaming_171/synth/altera_jtag_streaming.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_fpga_m/altera_jtag_dc_streaming_171/synth/altera_std_synchronizer_nocut.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_fpga_m/altera_reset_controller_171/synth/altera_reset_controller.sdc
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_fpga_m/altera_reset_controller_171/synth/altera_reset_controller.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_fpga_m/altera_reset_controller_171/synth/altera_reset_synchronizer.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_fpga_m/channel_adapter_171/synth/ghrd_10as066n2_fpga_m_channel_adapter_171_2swajja.sv
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_fpga_m/channel_adapter_171/synth/ghrd_10as066n2_fpga_m_channel_adapter_171_vh2yu6y.sv
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_fpga_m/ghrd_10as066n2_fpga_m.bsf
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_fpga_m/ghrd_10as066n2_fpga_m.cmp
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_fpga_m/ghrd_10as066n2_fpga_m.html
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_fpga_m/ghrd_10as066n2_fpga_m.qgsynthc
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_fpga_m/ghrd_10as066n2_fpga_m.qip
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_fpga_m/ghrd_10as066n2_fpga_m.sopcinfo
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_fpga_m/ghrd_10as066n2_fpga_m.xml
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_fpga_m/ghrd_10as066n2_fpga_m_bb.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_fpga_m/ghrd_10as066n2_fpga_m_generation.rpt
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_fpga_m/ghrd_10as066n2_fpga_m_generation_previous.rpt
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_fpga_m/ghrd_10as066n2_fpga_m_inst.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_fpga_m/ghrd_10as066n2_fpga_m_inst.vhd
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_fpga_m/synth/ghrd_10as066n2_fpga_m.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_fpga_m/timing_adapter_171/synth/ghrd_10as066n2_fpga_m_timing_adapter_171_xf5weri.sv
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_hps_m.ip
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_hps_m/altera_avalon_packets_to_master_171/synth/altera_avalon_packets_to_master.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_hps_m/altera_avalon_sc_fifo_171/synth/altera_avalon_sc_fifo.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_hps_m/altera_avalon_st_bytes_to_packets_171/synth/altera_avalon_st_bytes_to_packets.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_hps_m/altera_avalon_st_packets_to_bytes_171/synth/altera_avalon_st_packets_to_bytes.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_hps_m/altera_jtag_avalon_master_171/synth/ghrd_10as066n2_hps_m_altera_jtag_avalon_master_171_wqhllki.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_hps_m/altera_jtag_dc_streaming_171/synth/altera_avalon_st_clock_crosser.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_hps_m/altera_jtag_dc_streaming_171/synth/altera_avalon_st_idle_inserter.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_hps_m/altera_jtag_dc_streaming_171/synth/altera_avalon_st_idle_remover.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_hps_m/altera_jtag_dc_streaming_171/synth/altera_avalon_st_jtag_interface.sdc
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_hps_m/altera_jtag_dc_streaming_171/synth/altera_avalon_st_jtag_interface.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_hps_m/altera_jtag_dc_streaming_171/synth/altera_avalon_st_pipeline_base.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_hps_m/altera_jtag_dc_streaming_171/synth/altera_avalon_st_pipeline_stage.sv
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_hps_m/altera_jtag_dc_streaming_171/synth/altera_jtag_dc_streaming.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_hps_m/altera_jtag_dc_streaming_171/synth/altera_jtag_sld_node.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_hps_m/altera_jtag_dc_streaming_171/synth/altera_jtag_streaming.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_hps_m/altera_jtag_dc_streaming_171/synth/altera_std_synchronizer_nocut.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_hps_m/altera_reset_controller_171/synth/altera_reset_controller.sdc
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_hps_m/altera_reset_controller_171/synth/altera_reset_controller.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_hps_m/altera_reset_controller_171/synth/altera_reset_synchronizer.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_hps_m/channel_adapter_171/synth/ghrd_10as066n2_hps_m_channel_adapter_171_2swajja.sv
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_hps_m/channel_adapter_171/synth/ghrd_10as066n2_hps_m_channel_adapter_171_vh2yu6y.sv
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_hps_m/ghrd_10as066n2_hps_m.bsf
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_hps_m/ghrd_10as066n2_hps_m.cmp
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_hps_m/ghrd_10as066n2_hps_m.html
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_hps_m/ghrd_10as066n2_hps_m.qgsynthc
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_hps_m/ghrd_10as066n2_hps_m.qip
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_hps_m/ghrd_10as066n2_hps_m.sopcinfo
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_hps_m/ghrd_10as066n2_hps_m.xml
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_hps_m/ghrd_10as066n2_hps_m_bb.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_hps_m/ghrd_10as066n2_hps_m_generation.rpt
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_hps_m/ghrd_10as066n2_hps_m_generation_previous.rpt
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_hps_m/ghrd_10as066n2_hps_m_inst.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_hps_m/ghrd_10as066n2_hps_m_inst.vhd
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_hps_m/synth/ghrd_10as066n2_hps_m.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_hps_m/timing_adapter_171/synth/ghrd_10as066n2_hps_m_timing_adapter_171_xf5weri.sv
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_issp_0.ip
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_issp_0/altera_in_system_sources_probes_171/synth/altsource_probe_top.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_issp_0/ghrd_10as066n2_issp_0.bsf
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_issp_0/ghrd_10as066n2_issp_0.cmp
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_issp_0/ghrd_10as066n2_issp_0.html
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_issp_0/ghrd_10as066n2_issp_0.qgsynthc
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_issp_0/ghrd_10as066n2_issp_0.qip
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_issp_0/ghrd_10as066n2_issp_0.sopcinfo
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_issp_0/ghrd_10as066n2_issp_0.xml
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_issp_0/ghrd_10as066n2_issp_0_bb.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_issp_0/ghrd_10as066n2_issp_0_generation.rpt
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_issp_0/ghrd_10as066n2_issp_0_generation_previous.rpt
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_issp_0/ghrd_10as066n2_issp_0_inst.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_issp_0/ghrd_10as066n2_issp_0_inst.vhd
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_issp_0/synth/ghrd_10as066n2_issp_0.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_led_pio.ip
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_led_pio/altera_avalon_pio_171/synth/ghrd_10as066n2_led_pio_altera_avalon_pio_171_yz2rppa.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_led_pio/ghrd_10as066n2_led_pio.bsf
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_led_pio/ghrd_10as066n2_led_pio.cmp
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_led_pio/ghrd_10as066n2_led_pio.html
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_led_pio/ghrd_10as066n2_led_pio.qgsynthc
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_led_pio/ghrd_10as066n2_led_pio.qip
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_led_pio/ghrd_10as066n2_led_pio.regmap
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_led_pio/ghrd_10as066n2_led_pio.sopcinfo
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_led_pio/ghrd_10as066n2_led_pio.xml
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_led_pio/ghrd_10as066n2_led_pio_bb.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_led_pio/ghrd_10as066n2_led_pio_generation.rpt
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_led_pio/ghrd_10as066n2_led_pio_generation_previous.rpt
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_led_pio/ghrd_10as066n2_led_pio_inst.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_led_pio/ghrd_10as066n2_led_pio_inst.vhd
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_led_pio/synth/ghrd_10as066n2_led_pio.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_merlin_axi_translator_0/ghrd_10as066n2_merlin_axi_translator_0_generation.rpt
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_mm_bridge_0.ip
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_mm_bridge_0/altera_avalon_mm_bridge_171/synth/altera_avalon_mm_bridge.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_mm_bridge_0/ghrd_10as066n2_mm_bridge_0.bsf
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_mm_bridge_0/ghrd_10as066n2_mm_bridge_0.cmp
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_mm_bridge_0/ghrd_10as066n2_mm_bridge_0.html
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_mm_bridge_0/ghrd_10as066n2_mm_bridge_0.qgsynthc
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_mm_bridge_0/ghrd_10as066n2_mm_bridge_0.qip
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_mm_bridge_0/ghrd_10as066n2_mm_bridge_0.sopcinfo
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_mm_bridge_0/ghrd_10as066n2_mm_bridge_0.xml
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_mm_bridge_0/ghrd_10as066n2_mm_bridge_0_bb.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_mm_bridge_0/ghrd_10as066n2_mm_bridge_0_generation.rpt
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_mm_bridge_0/ghrd_10as066n2_mm_bridge_0_generation_previous.rpt
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_mm_bridge_0/ghrd_10as066n2_mm_bridge_0_inst.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_mm_bridge_0/ghrd_10as066n2_mm_bridge_0_inst.vhd
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_mm_bridge_0/synth/ghrd_10as066n2_mm_bridge_0.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_ocm_0.ip
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_ocm_0/altera_avalon_onchip_memory2_171/synth/ghrd_10as066n2_ocm_0_altera_avalon_onchip_memory2_171_ehvj5ii.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_ocm_0/altera_avalon_onchip_memory2_171/synth/ghrd_10as066n2_ocm_0_ocm_0.hex
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_ocm_0/ghrd_10as066n2_ocm_0.bsf
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_ocm_0/ghrd_10as066n2_ocm_0.cmp
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_ocm_0/ghrd_10as066n2_ocm_0.html
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_ocm_0/ghrd_10as066n2_ocm_0.qgsynthc
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_ocm_0/ghrd_10as066n2_ocm_0.qip
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_ocm_0/ghrd_10as066n2_ocm_0.sopcinfo
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_ocm_0/ghrd_10as066n2_ocm_0.xml
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_ocm_0/ghrd_10as066n2_ocm_0_bb.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_ocm_0/ghrd_10as066n2_ocm_0_generation.rpt
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_ocm_0/ghrd_10as066n2_ocm_0_generation_previous.rpt
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_ocm_0/ghrd_10as066n2_ocm_0_inst.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_ocm_0/ghrd_10as066n2_ocm_0_inst.vhd
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_ocm_0/synth/ghrd_10as066n2_ocm_0.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_pb_lwh2f.ip
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_pb_lwh2f/altera_avalon_mm_bridge_171/synth/altera_avalon_mm_bridge.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_pb_lwh2f/ghrd_10as066n2_pb_lwh2f.bsf
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_pb_lwh2f/ghrd_10as066n2_pb_lwh2f.cmp
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_pb_lwh2f/ghrd_10as066n2_pb_lwh2f.html
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_pb_lwh2f/ghrd_10as066n2_pb_lwh2f.qgsynthc
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_pb_lwh2f/ghrd_10as066n2_pb_lwh2f.qip
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_pb_lwh2f/ghrd_10as066n2_pb_lwh2f.sopcinfo
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_pb_lwh2f/ghrd_10as066n2_pb_lwh2f.xml
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_pb_lwh2f/ghrd_10as066n2_pb_lwh2f_bb.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_pb_lwh2f/ghrd_10as066n2_pb_lwh2f_generation.rpt
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_pb_lwh2f/ghrd_10as066n2_pb_lwh2f_generation_previous.rpt
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_pb_lwh2f/ghrd_10as066n2_pb_lwh2f_inst.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_pb_lwh2f/ghrd_10as066n2_pb_lwh2f_inst.vhd
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_pb_lwh2f/synth/ghrd_10as066n2_pb_lwh2f.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_pr_region_controller_0.ip
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_pr_region_controller_0/altera_conduit_merger_171/synth/ghrd_10as066n2_pr_region_controller_0_altera_conduit_merger_171_nva7cjy.sv
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_pr_region_controller_0/altera_freeze_control_171/synth/altera_freeze_control.sv
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_pr_region_controller_0/altera_freeze_csr_171/synth/altera_freeze_csr.sv
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_pr_region_controller_0/altera_pr_region_controller_171/synth/ghrd_10as066n2_pr_region_controller_0_altera_pr_region_controller_171_lvntgla.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_pr_region_controller_0/ghrd_10as066n2_pr_region_controller_0.bsf
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_pr_region_controller_0/ghrd_10as066n2_pr_region_controller_0.cmp
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_pr_region_controller_0/ghrd_10as066n2_pr_region_controller_0.html
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_pr_region_controller_0/ghrd_10as066n2_pr_region_controller_0.qgsynthc
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_pr_region_controller_0/ghrd_10as066n2_pr_region_controller_0.qip
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_pr_region_controller_0/ghrd_10as066n2_pr_region_controller_0.regmap
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_pr_region_controller_0/ghrd_10as066n2_pr_region_controller_0.sopcinfo
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_pr_region_controller_0/ghrd_10as066n2_pr_region_controller_0.xml
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_pr_region_controller_0/ghrd_10as066n2_pr_region_controller_0_bb.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_pr_region_controller_0/ghrd_10as066n2_pr_region_controller_0_generation.rpt
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_pr_region_controller_0/ghrd_10as066n2_pr_region_controller_0_generation_previous.rpt
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_pr_region_controller_0/ghrd_10as066n2_pr_region_controller_0_inst.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_pr_region_controller_0/ghrd_10as066n2_pr_region_controller_0_inst.vhd
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_pr_region_controller_0/synth/ghrd_10as066n2_pr_region_controller_0.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_rst_bdg.ip
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_rst_bdg/ghrd_10as066n2_rst_bdg.bsf
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_rst_bdg/ghrd_10as066n2_rst_bdg.cmp
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_rst_bdg/ghrd_10as066n2_rst_bdg.html
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_rst_bdg/ghrd_10as066n2_rst_bdg.qgsynthc
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_rst_bdg/ghrd_10as066n2_rst_bdg.qip
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_rst_bdg/ghrd_10as066n2_rst_bdg.sopcinfo
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_rst_bdg/ghrd_10as066n2_rst_bdg.xml
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_rst_bdg/ghrd_10as066n2_rst_bdg_bb.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_rst_bdg/ghrd_10as066n2_rst_bdg_generation.rpt
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_rst_bdg/ghrd_10as066n2_rst_bdg_generation_previous.rpt
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_rst_bdg/ghrd_10as066n2_rst_bdg_inst.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_rst_bdg/ghrd_10as066n2_rst_bdg_inst.vhd
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_rst_bdg/synth/ghrd_10as066n2_rst_bdg.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_rst_in.ip
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_rst_in/ghrd_10as066n2_rst_in.bsf
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_rst_in/ghrd_10as066n2_rst_in.cmp
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_rst_in/ghrd_10as066n2_rst_in.html
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_rst_in/ghrd_10as066n2_rst_in.qgsynthc
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_rst_in/ghrd_10as066n2_rst_in.qip
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_rst_in/ghrd_10as066n2_rst_in.sopcinfo
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_rst_in/ghrd_10as066n2_rst_in.xml
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_rst_in/ghrd_10as066n2_rst_in_bb.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_rst_in/ghrd_10as066n2_rst_in_generation.rpt
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_rst_in/ghrd_10as066n2_rst_in_generation_previous.rpt
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_rst_in/ghrd_10as066n2_rst_in_inst.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_rst_in/ghrd_10as066n2_rst_in_inst.vhd
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_rst_in/synth/ghrd_10as066n2_rst_in.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_sys_id.ip
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_sys_id/altera_avalon_sysid_qsys_171/synth/altera_avalon_sysid_qsys.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_sys_id/ghrd_10as066n2_sys_id.bsf
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_sys_id/ghrd_10as066n2_sys_id.cmp
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_sys_id/ghrd_10as066n2_sys_id.html
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_sys_id/ghrd_10as066n2_sys_id.qgsynthc
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_sys_id/ghrd_10as066n2_sys_id.qip
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_sys_id/ghrd_10as066n2_sys_id.regmap
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_sys_id/ghrd_10as066n2_sys_id.sopcinfo
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_sys_id/ghrd_10as066n2_sys_id.xml
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_sys_id/ghrd_10as066n2_sys_id_bb.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_sys_id/ghrd_10as066n2_sys_id_generation.rpt
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_sys_id/ghrd_10as066n2_sys_id_generation_previous.rpt
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_sys_id/ghrd_10as066n2_sys_id_inst.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_sys_id/ghrd_10as066n2_sys_id_inst.vhd
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_sys_id/synth/ghrd_10as066n2_sys_id.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pdo/pdo.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_alternate/.qsys_edit/filters.xml
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_alternate/.qsys_edit/preferences.xml
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_alternate/pr_region_alternate_Top_DUT_0.ip
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_alternate/pr_region_alternate_clock_in.ip
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_alternate/pr_region_alternate_clock_in/pr_region_alternate_clock_in.bsf
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_alternate/pr_region_alternate_clock_in/pr_region_alternate_clock_in.cmp
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_alternate/pr_region_alternate_clock_in/pr_region_alternate_clock_in.html
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_alternate/pr_region_alternate_clock_in/pr_region_alternate_clock_in.qgsynthc
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_alternate/pr_region_alternate_clock_in/pr_region_alternate_clock_in.qip
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_alternate/pr_region_alternate_clock_in/pr_region_alternate_clock_in.sopcinfo
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_alternate/pr_region_alternate_clock_in/pr_region_alternate_clock_in.xml
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_alternate/pr_region_alternate_clock_in/pr_region_alternate_clock_in_bb.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_alternate/pr_region_alternate_clock_in/pr_region_alternate_clock_in_generation.rpt
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_alternate/pr_region_alternate_clock_in/pr_region_alternate_clock_in_generation_previous.rpt
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_alternate/pr_region_alternate_clock_in/pr_region_alternate_clock_in_inst.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_alternate/pr_region_alternate_clock_in/pr_region_alternate_clock_in_inst.vhd
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_alternate/pr_region_alternate_clock_in/synth/pr_region_alternate_clock_in.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_alternate/pr_region_alternate_mm_bridge_0.ip
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_alternate/pr_region_alternate_mm_bridge_0/altera_avalon_mm_bridge_171/synth/altera_avalon_mm_bridge.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_alternate/pr_region_alternate_mm_bridge_0/pr_region_alternate_mm_bridge_0.bsf
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_alternate/pr_region_alternate_mm_bridge_0/pr_region_alternate_mm_bridge_0.cmp
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_alternate/pr_region_alternate_mm_bridge_0/pr_region_alternate_mm_bridge_0.html
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_alternate/pr_region_alternate_mm_bridge_0/pr_region_alternate_mm_bridge_0.qgsynthc
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_alternate/pr_region_alternate_mm_bridge_0/pr_region_alternate_mm_bridge_0.qip
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_alternate/pr_region_alternate_mm_bridge_0/pr_region_alternate_mm_bridge_0.sopcinfo
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_alternate/pr_region_alternate_mm_bridge_0/pr_region_alternate_mm_bridge_0.xml
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_alternate/pr_region_alternate_mm_bridge_0/pr_region_alternate_mm_bridge_0_bb.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_alternate/pr_region_alternate_mm_bridge_0/pr_region_alternate_mm_bridge_0_generation.rpt
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_alternate/pr_region_alternate_mm_bridge_0/pr_region_alternate_mm_bridge_0_generation_previous.rpt
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_alternate/pr_region_alternate_mm_bridge_0/pr_region_alternate_mm_bridge_0_inst.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_alternate/pr_region_alternate_mm_bridge_0/pr_region_alternate_mm_bridge_0_inst.vhd
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_alternate/pr_region_alternate_mm_bridge_0/synth/pr_region_alternate_mm_bridge_0.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_alternate/pr_region_alternate_reset_in.ip
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_alternate/pr_region_alternate_reset_in/pr_region_alternate_reset_in.bsf
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_alternate/pr_region_alternate_reset_in/pr_region_alternate_reset_in.cmp
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_alternate/pr_region_alternate_reset_in/pr_region_alternate_reset_in.html
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_alternate/pr_region_alternate_reset_in/pr_region_alternate_reset_in.qgsynthc
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_alternate/pr_region_alternate_reset_in/pr_region_alternate_reset_in.qip
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_alternate/pr_region_alternate_reset_in/pr_region_alternate_reset_in.sopcinfo
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_alternate/pr_region_alternate_reset_in/pr_region_alternate_reset_in.xml
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_alternate/pr_region_alternate_reset_in/pr_region_alternate_reset_in_bb.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_alternate/pr_region_alternate_reset_in/pr_region_alternate_reset_in_generation.rpt
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_alternate/pr_region_alternate_reset_in/pr_region_alternate_reset_in_generation_previous.rpt
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_alternate/pr_region_alternate_reset_in/pr_region_alternate_reset_in_inst.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_alternate/pr_region_alternate_reset_in/pr_region_alternate_reset_in_inst.vhd
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_alternate/pr_region_alternate_reset_in/synth/pr_region_alternate_reset_in.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_alternate/pr_region_alternate_sysid_qsys_0.ip
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_alternate/pr_region_alternate_sysid_qsys_0/altera_avalon_sysid_qsys_171/synth/altera_avalon_sysid_qsys.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_alternate/pr_region_alternate_sysid_qsys_0/pr_region_alternate_sysid_qsys_0.bsf
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_alternate/pr_region_alternate_sysid_qsys_0/pr_region_alternate_sysid_qsys_0.cmp
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_alternate/pr_region_alternate_sysid_qsys_0/pr_region_alternate_sysid_qsys_0.html
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_alternate/pr_region_alternate_sysid_qsys_0/pr_region_alternate_sysid_qsys_0.qgsynthc
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_alternate/pr_region_alternate_sysid_qsys_0/pr_region_alternate_sysid_qsys_0.qip
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_alternate/pr_region_alternate_sysid_qsys_0/pr_region_alternate_sysid_qsys_0.regmap
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_alternate/pr_region_alternate_sysid_qsys_0/pr_region_alternate_sysid_qsys_0.sopcinfo
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_alternate/pr_region_alternate_sysid_qsys_0/pr_region_alternate_sysid_qsys_0.xml
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_alternate/pr_region_alternate_sysid_qsys_0/pr_region_alternate_sysid_qsys_0_bb.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_alternate/pr_region_alternate_sysid_qsys_0/pr_region_alternate_sysid_qsys_0_generation.rpt
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_alternate/pr_region_alternate_sysid_qsys_0/pr_region_alternate_sysid_qsys_0_generation_previous.rpt
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_alternate/pr_region_alternate_sysid_qsys_0/pr_region_alternate_sysid_qsys_0_inst.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_alternate/pr_region_alternate_sysid_qsys_0/pr_region_alternate_sysid_qsys_0_inst.vhd
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_alternate/pr_region_alternate_sysid_qsys_0/synth/pr_region_alternate_sysid_qsys_0.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_Top_0.ip
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_Top_0/Top_10/synth/Top.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_Top_0/pr_region_default_Top_0.bsf
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_Top_0/pr_region_default_Top_0.cmp
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_Top_0/pr_region_default_Top_0.html
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_Top_0/pr_region_default_Top_0.qgsynthc
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_Top_0/pr_region_default_Top_0.qip
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_Top_0/pr_region_default_Top_0.sopcinfo
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_Top_0/pr_region_default_Top_0.xml
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_Top_0/pr_region_default_Top_0_bb.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_Top_0/pr_region_default_Top_0_generation.rpt
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_Top_0/pr_region_default_Top_0_generation_previous.rpt
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_Top_0/pr_region_default_Top_0_inst.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_Top_0/pr_region_default_Top_0_inst.vhd
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_Top_0/synth/pr_region_default_Top_0.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_clock_in.ip
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_clock_in/pr_region_default_clock_in.bsf
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_clock_in/pr_region_default_clock_in.cmp
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_clock_in/pr_region_default_clock_in.html
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_clock_in/pr_region_default_clock_in.qgsynthc
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_clock_in/pr_region_default_clock_in.qip
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_clock_in/pr_region_default_clock_in.sopcinfo
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_clock_in/pr_region_default_clock_in.xml
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_clock_in/pr_region_default_clock_in_bb.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_clock_in/pr_region_default_clock_in_generation.rpt
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_clock_in/pr_region_default_clock_in_generation_previous.rpt
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_clock_in/pr_region_default_clock_in_inst.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_clock_in/pr_region_default_clock_in_inst.vhd
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_clock_in/synth/pr_region_default_clock_in.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_mm_bridge_0.ip
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_mm_bridge_0/altera_avalon_mm_bridge_171/synth/altera_avalon_mm_bridge.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_mm_bridge_0/pr_region_default_mm_bridge_0.bsf
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_mm_bridge_0/pr_region_default_mm_bridge_0.cmp
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_mm_bridge_0/pr_region_default_mm_bridge_0.html
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_mm_bridge_0/pr_region_default_mm_bridge_0.qgsynthc
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_mm_bridge_0/pr_region_default_mm_bridge_0.qip
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_mm_bridge_0/pr_region_default_mm_bridge_0.sopcinfo
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_mm_bridge_0/pr_region_default_mm_bridge_0.xml
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_mm_bridge_0/pr_region_default_mm_bridge_0_bb.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_mm_bridge_0/pr_region_default_mm_bridge_0_generation.rpt
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_mm_bridge_0/pr_region_default_mm_bridge_0_generation_previous.rpt
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_mm_bridge_0/pr_region_default_mm_bridge_0_inst.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_mm_bridge_0/pr_region_default_mm_bridge_0_inst.vhd
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_mm_bridge_0/synth/pr_region_default_mm_bridge_0.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_mm_bridge_1/altera_avalon_mm_bridge_171/synth/altera_avalon_mm_bridge.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_mm_bridge_1/pr_region_default_mm_bridge_1.bsf
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_mm_bridge_1/pr_region_default_mm_bridge_1.cmp
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_mm_bridge_1/pr_region_default_mm_bridge_1.html
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_mm_bridge_1/pr_region_default_mm_bridge_1.qgsynthc
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_mm_bridge_1/pr_region_default_mm_bridge_1.qip
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_mm_bridge_1/pr_region_default_mm_bridge_1.sopcinfo
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_mm_bridge_1/pr_region_default_mm_bridge_1.xml
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_mm_bridge_1/pr_region_default_mm_bridge_1_bb.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_mm_bridge_1/pr_region_default_mm_bridge_1_generation.rpt
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_mm_bridge_1/pr_region_default_mm_bridge_1_inst.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_mm_bridge_1/pr_region_default_mm_bridge_1_inst.vhd
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_mm_bridge_1/synth/pr_region_default_mm_bridge_1.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_onchip_memory2_0.ip
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_onchip_memory2_0/altera_avalon_onchip_memory2_171/synth/pr_region_default_onchip_memory2_0_altera_avalon_onchip_memory2_171_z7z2goy.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_onchip_memory2_0/pr_region_default_onchip_memory2_0.bsf
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_onchip_memory2_0/pr_region_default_onchip_memory2_0.cmp
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_onchip_memory2_0/pr_region_default_onchip_memory2_0.html
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_onchip_memory2_0/pr_region_default_onchip_memory2_0.qgsynthc
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_onchip_memory2_0/pr_region_default_onchip_memory2_0.qip
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_onchip_memory2_0/pr_region_default_onchip_memory2_0.sopcinfo
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_onchip_memory2_0/pr_region_default_onchip_memory2_0.xml
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_onchip_memory2_0/pr_region_default_onchip_memory2_0_bb.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_onchip_memory2_0/pr_region_default_onchip_memory2_0_generation.rpt
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_onchip_memory2_0/pr_region_default_onchip_memory2_0_inst.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_onchip_memory2_0/pr_region_default_onchip_memory2_0_inst.vhd
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_onchip_memory2_0/synth/pr_region_default_onchip_memory2_0.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_reset_in.ip
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_reset_in/pr_region_default_reset_in.bsf
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_reset_in/pr_region_default_reset_in.cmp
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_reset_in/pr_region_default_reset_in.html
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_reset_in/pr_region_default_reset_in.qgsynthc
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_reset_in/pr_region_default_reset_in.qip
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_reset_in/pr_region_default_reset_in.sopcinfo
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_reset_in/pr_region_default_reset_in.xml
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_reset_in/pr_region_default_reset_in_bb.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_reset_in/pr_region_default_reset_in_generation.rpt
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_reset_in/pr_region_default_reset_in_generation_previous.rpt
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_reset_in/pr_region_default_reset_in_inst.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_reset_in/pr_region_default_reset_in_inst.vhd
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_reset_in/synth/pr_region_default_reset_in.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_sysid_qsys_0.ip
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_sysid_qsys_0/altera_avalon_sysid_qsys_171/synth/altera_avalon_sysid_qsys.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_sysid_qsys_0/pr_region_default_sysid_qsys_0.bsf
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_sysid_qsys_0/pr_region_default_sysid_qsys_0.cmp
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_sysid_qsys_0/pr_region_default_sysid_qsys_0.html
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_sysid_qsys_0/pr_region_default_sysid_qsys_0.qgsynthc
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_sysid_qsys_0/pr_region_default_sysid_qsys_0.qip
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_sysid_qsys_0/pr_region_default_sysid_qsys_0.regmap
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_sysid_qsys_0/pr_region_default_sysid_qsys_0.sopcinfo
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_sysid_qsys_0/pr_region_default_sysid_qsys_0.xml
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_sysid_qsys_0/pr_region_default_sysid_qsys_0_bb.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_sysid_qsys_0/pr_region_default_sysid_qsys_0_generation.rpt
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_sysid_qsys_0/pr_region_default_sysid_qsys_0_generation_previous.rpt
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_sysid_qsys_0/pr_region_default_sysid_qsys_0_inst.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_sysid_qsys_0/pr_region_default_sysid_qsys_0_inst.vhd
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_sysid_qsys_0/synth/pr_region_default_sysid_qsys_0.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/vesa_tpg/vesa_tpg.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/vesa_tpg/vesa_tpg_hw.tcl
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/jtag.sdc
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/pr_alternate_fit.qsf
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/pr_alternate_fit.qws
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/pr_alternate_fit_description.txt
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/pr_alternate_synth.done
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/pr_alternate_synth.qsf
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/pr_alternate_synth.qws
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/pr_alternate_synth_description.txt
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/pr_base.qsf
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/pr_base.qws
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/pr_base_description.txt
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/pr_region_alternate.qsys
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/pr_region_default.qsys
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/pr_region_default.qsysquartus_sh_tcl_file_for_qsyspro.tcl
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/qdb/_compiler/pr_alternate_fit/_flat/17.1.0/legacy/1/pr_alternate_fit.db_info
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/qdb/_compiler/pr_alternate_synth/_flat/17.1.0/legacy/1/pr_alternate_synth.db_info
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/qdb/_compiler/pr_base/_flat/17.1.0/legacy/1/pr_base.db_info
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/quartus_sh_tcl_file_for_qsyspro.tcl
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/top_level_template.v.terp
A spatial/core/resources/chiselgen/template-level/fringeArria10/build/update_sysid.tcl
A spatial/core/resources/chiselgen/template-level/fringeArria10/testbenches/Arria10_tb.v
A spatial/core/resources/chiselgen/template-level/fringeArria10/testbenches/simulate.sh
M spatial/core/resources/chiselgen/template-level/fringeHW/CommonMain.scala
M spatial/core/resources/chiselgen/template-level/fringeHW/FringeDE1SoC.scala
M spatial/core/resources/chiselgen/template-level/fringeHW/MAGCore.scala
M spatial/core/resources/chiselgen/template-level/fringeHW/SRAM.scala
M spatial/core/resources/chiselgen/template-level/fringeHW/axi4/Bundles.scala
A spatial/core/resources/cppgen/fringeArria10/Arria10AddressMap.h
A spatial/core/resources/cppgen/fringeArria10/Arria10Utils.cpp
A spatial/core/resources/cppgen/fringeArria10/Arria10Utils.h
A spatial/core/resources/cppgen/fringeArria10/FringeContext.h
A spatial/core/resources/cppgen/fringeArria10/FringeContextArria10.h
A spatial/core/resources/cppgen/fringeArria10/FringeContextBase.h
A spatial/core/resources/cppgen/fringeArria10/Makefile
A spatial/core/resources/cppgen/fringeArria10/utils/run.sh
A spatial/core/resources/cppgen/fringeArria10/utils/setClocks.sh
A spatial/core/resources/cppgen/fringeArria10/utils/set_perms
M spatial/core/resources/files_list
commit acc09897305e2b895c9eabc3b234486c53e5470e
Author: Matthew Feldman <[email protected]>
Date: Mon Jan 22 19:45:07 2018 -0800
fix mismatch between loopbacks
M spatial/core/resources/chiselgen/app-level/Top.scala
M spatial/core/resources/chiselgen/template-level/fringeHW/Fringe.scala
M spatial/core/resources/chiselgen/template-level/fringeHW/FringeGlobals.scala
M spatial/core/resources/chiselgen/template-level/fringeHW/FringeZynq.scala
M spatial/core/resources/chiselgen/template-level/fringeHW/RegFile.scala
commit 7f3776b3e2bb1c2d69a5e0a589a309cc697df90a
Author: Matthew Feldman <[email protected]>
Date: Mon Jan 22 19:22:44 2018 -0800
add support for arria10 regression and fix argout loopback
M apps
M argon
M spatial/core/resources/chiselgen/app-level/Top.scala
M spatial/core/resources/chiselgen/app-level/scripts/report.py
M spatial/core/resources/chiselgen/app-level/scripts/scrape.py
M spatial/core/resources/chiselgen/app-level/scripts/scrape.sh
M spatial/core/resources/chiselgen/template-level/fringeHW/Fringe.scala
M spatial/core/resources/chiselgen/template-level/fringeHW/FringeDE1SoC.scala
M spatial/core/resources/chiselgen/template-level/fringeHW/FringeZynq.scala
M spatial/core/resources/chiselgen/template-level/fringeHW/MAGCore.scala
M spatial/core/resources/chiselgen/template-level/fringeHW/RegFile.scala
M spatial/core/resources/chiselgen/template-level/fringeZynq/build/bdproject.tcl
M spatial/core/src/spatial/codegen/chiselgen/ChiselGenReg.scala
M utilities/synth_regression.sh
M utilities/tid.py
commit 5e46f1239013966eab638b52fae098e0791ad3e5
Author: Matthew Feldman <[email protected]>
Date: Sun Jan 21 09:45:39 2018 -0800
make Regression file happy
M apps
commit d07969a242744972e49b4b54f4da6509bfea890d
Author: Matthew Feldman <[email protected]>
Date: Sat Jan 20 14:30:58 2018 -0800
fix bug #255, do unalignedstore/load statistics checks properly with metadata, fix missing method for %-% in Utils, fix regression statistics reporter
M apps
M spatial/core/resources/chiselgen/app-level/scripts/regression_report.py
M spatial/core/resources/chiselgen/template-level/templates/Utils.scala
M spatial/core/src/spatial/codegen/chiselgen/ChiselGenDRAM.scala
M spatial/core/src/spatial/codegen/chiselgen/ChiselGenReg.scala
M spatial/core/src/spatial/lang/DRAMTransfersInternal.scala
M spatial/core/src/spatial/metadata/SpatialMetadata.scala
Argon commit
commit ce91373df000c88b96f3cdaacd13825f02161683
Author: Matthew Feldman <[email protected]>
Date: Mon Jan 22 19:52:20 2018 -0800
add asic back in
M core/src/argon/codegen/chiselgen/ChiselCodegen.scala
Virtualized commit
commit 1a5adc8e9cd171f1a8c3f1f66dddbc04d89aa51f
Author: David Koeplinger <[email protected]>
Date: Fri Jul 21 17:15:08 2017 -0700
fix mistake in Structs
M src/org/virtualized/Structs.scala
Spatial-Apps commit
commit b8b21d7e53eb8948d6cb868bdd8d8f5ca70932c0
Author: Matthew Feldman <[email protected]>
Date: Tue Jan 23 10:34:38 2018 -0800
add second mem to make pageboundarytest harder
M src/UnitTests.scala
Creation Time- 2018-01-23_10-36-35 | Status- debug | Type- chisel | tests- all | User- mattfel | Origin- london | Destination- london | Branch- master | Spatial- 9b765 | Argon- ce913 | Virtualized- 1a5ad | Spatial-apps- b8b21