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This repository has been archived by the owner on Dec 1, 2018. It is now read-only.
We already made a lot of progress on getting this functionality through the connectDbgSig in MAGCore, we just need another kind of debug port that logs values to an sram for each cycle, probably with a start and end trigger. This will also require a new axi interface for interrogating each value in the sram after execution. This seems like a project that would have a lot of value for us and spatial users and has a relatively sealed scope that would be a good fit for a new student who is interested in learning about fringe, verilog, and the overall ip architecture
The text was updated successfully, but these errors were encountered:
It might be worth spending some time to define our own target-agnostic API to enable viewing signals from the board to host. We can then choose to implement the API using either our own modules or using ILA cores from vendors.
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We already made a lot of progress on getting this functionality through the connectDbgSig in MAGCore, we just need another kind of debug port that logs values to an sram for each cycle, probably with a start and end trigger. This will also require a new axi interface for interrogating each value in the sram after execution. This seems like a project that would have a lot of value for us and spatial users and has a relatively sealed scope that would be a good fit for a new student who is interested in learning about fringe, verilog, and the overall ip architecture
The text was updated successfully, but these errors were encountered: