Minor fix in systems appendix

src/system.adoc

@@ -44,7 +44,7 @@ All writes from the system port to the memory must clear any memory tags to foll
 image::large_cheri_system.drawio.png[width=80%,align=center]
 
 In the case of a large CHERI SoC with caches, all the cached memory visible to the CHERI CPUs must support tags.
-All memory is backed up by DRAM, and standard DRAM does not offer 129-bit words and so a typical system will have a tag cache IP.
+All memory is backed up by DRAM, and standard DRAM does not offer CLEN+1 bit words and so a typical system will have a tag cache IP.
 
 A region of DRAM is reserved for CHERI tag storage.