Minor grammatical fixes in tid extension chapter

src/tid-ext.adoc

@@ -77,10 +77,10 @@ include::img/stidreg.edn[]
 The <<vstid>> register is a VSLEN-bit read-write register. It is VS-mode's
 version of supervisor register <<stid>> used to identify the current
 thread in virtual supervisor mode. As other Virtual Supervisor registers
-when V=1, <<vstid>> substitutes for the usual <<stid>>, so that
+when V=1, <<vstid>> substitutes for <<stid>>, so that
 instructions that normally read or modify <<stid>> actually access
 <<vstid>> instead. When V=0, <<vstid>> does not directly affect the
-behaviour of the machine.
+behavior of the machine.
 
 The reset value of this register is UNSPECIFIED.
 
@@ -128,13 +128,13 @@ include::img/stidcreg.edn[]
 ==== Virtual Supervisor Thread Identifier Capability (vstidc)
 
 The <<vstidc>> register is a CLEN-bit read-write capability register.
-It is the capability extension of the <<stidc>> register used to
+It is the capability extension of the <<vstid>> register used to
 identify the current thread in virtual supervisor mode.
 As other Virtual Supervisor registers when V=1, <<vstidc>> substitutes
-for the usual <<stidc>>, so that instructions that normally read or modify
+for <<stidc>>, so that instructions that normally read or modify
 <<stidc>> actually access <<vstidc>> instead.
 When V=0, <<vstidc>> does not directly affect the
-behaviour of the machine.
+behavior of the machine.
 On reset the tag of <<vstidc>> will be set to 0 and the remainder
 of the data is UNSPECIFIED.
 
@@ -229,11 +229,11 @@ overhead of this is not bearable for CHERI systems with many compartments.
 The RISC-V ABI includes a _thread pointer (tp)_ register, which is not
 usable for the purpose of reliably identifying the current thread because
 the tp register is a general purpose register and can be changed arbitrarily
-by untrusted code. Therefore, this specification offers three additional CSRs
+by untrusted code. Therefore, this specification offers additional CSRs
 that facilitate a trusted source for the thread ID. All registers are readable
 from their respective privilege levels and writeable with <<asr_perm>>.
 
 This extension extends <<mtid>>, <<stid>>, <<vstid>> and <<utid>> to their respective
 capability variants <<mtidc>>, <<stidc>>, <<vstidc>> and <<utidc>>. This presents software with the
 freedom to still use these registers with capabilities or leave the metadata
-untouched and only use the registers to storage integers.
+untouched and only use the registers to store integers.