SPI-Slave-with-Single-Port-RAM

Designing SPI Slave with Single Port RAM using Questasim and Vivado.

The PDF file will have snippets of the following:

1. Snippets from the waveforms captured from QuestaSim for the design with inputs assigned values and output values visible.
2. Synthesis snippets for each encoding • Schematic after the elaboration & synthesis • Synthesis report showing the encoding used • Timing report snippet • Snippet of the critical path highlighted in the schematic
3. Implementation snippets for each encoding • Utilization report • Timing report snippet • FPGA device snippet
4. Snippet of the “Messages” tab showing no critical warnings or errors after running elaboration, synthesis, implementation and a successful bitstream generation.