Designing SPI Slave with Single Port RAM using Questasim and Vivado.
The PDF file will have snippets of the following:
- Snippets from the waveforms captured from QuestaSim for the design with inputs assigned values and output values visible.
- Synthesis snippets for each encoding • Schematic after the elaboration & synthesis • Synthesis report showing the encoding used • Timing report snippet • Snippet of the critical path highlighted in the schematic
- Implementation snippets for each encoding • Utilization report • Timing report snippet • FPGA device snippet
- Snippet of the “Messages” tab showing no critical warnings or errors after running elaboration, synthesis, implementation and a successful bitstream generation.