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update ci test set with supported buses
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Original file line number | Diff line number | Diff line change |
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@@ -1,22 +1,38 @@ | ||
- name: EF_GPIO8 | ||
url: https://github.com/efabless/EF_GPIO8.git | ||
tests: | ||
- gpio8_all_out_test gpio8_all_in_test | ||
- gpio8_all_out_test gpio8_all_in_test | ||
bus: | ||
- APB | ||
- AHBL | ||
- WB | ||
- name: EF_UART | ||
url: https://github.com/efabless/EF_UART.git | ||
tests: | ||
- TX_StressTest RX_StressTest LoopbackTest PrescalarStressTest | ||
- LengthParityTXStressTest LengthParityRXStressTest WriteReadRegsTest | ||
- TX_StressTest RX_StressTest LoopbackTest PrescalarStressTest | ||
- LengthParityTXStressTest LengthParityRXStressTest WriteReadRegsTest | ||
bus: | ||
- APB | ||
- AHBL | ||
- WB | ||
- name: EF_TMR32 | ||
url: https://github.com/efabless/EF_TMR32.git | ||
tests: | ||
- pwm_actions_test time_vary_test | ||
- pwm_pr_test pwm_tmr_test | ||
- pwm_actions_test time_vary_test | ||
- pwm_pr_test pwm_tmr_test | ||
bus: | ||
- APB | ||
- AHBL | ||
- WB | ||
- name: MS_QSPI_XIP_CACHE | ||
url: https://github.com/efabless/MS_QSPI_XIP_CACHE.git | ||
tests: | ||
- flashReadTest flashResetTest flashRdWrTest | ||
- flashReadTest flashResetTest flashRdWrTest | ||
bus: | ||
- AHBL | ||
- name: OL-DFFRAM | ||
url: https://github.com/efabless/OL-DFFRAM.git | ||
tests: | ||
- dffram_wr_rd_test dffram_corners_test | ||
- dffram_wr_rd_test dffram_corners_test | ||
bus: | ||
- AHBL |