Merge remote-tracking branch 'origin/main' into pretty-ci

bus_env/bus_agent/bus_ahb_driver.py

@@ -62,6 +62,8 @@ async def data_phase(self, tr):
             await self.drive_delay()
             while self.vif.HREADYOUT == 0:
                 await self.drive_delay()
+            tr.data = self.vif.HRDATA.value.integer
+        self.seq_item_port.put_response(tr)
 
     def end_of_trans(self):
         self.vif.HSEL.value = 0b00

bus_env/bus_agent/bus_apb_driver.py

@@ -41,32 +41,35 @@ async def run_phase(self, phase):
             # uvm_do_callbacks(apb_master,apb_master_cbs,trans_received(self,tr))
 
             if tr.kind == bus_item.READ:
-                data = []
-                await self.read(tr.addr, data)
-                tr.data = data[0]
+                tr.data = await self.read(tr.addr)
             elif tr.kind == bus_item.WRITE:
                 await self.write(tr.addr, tr.data)
 
             await self.trans_executed(tr)
             # uvm_do_callbacks(apb_master,apb_master_cbs,trans_executed(self,tr))
             self.seq_item_port.item_done()
+            self.seq_item_port.put_response(tr)
 
     async def trans_received(self, tr):
         await Timer(1, "NS")
 
     async def trans_executed(self, tr):
         await Timer(1, "NS")
 
-    async def read(self, addr, data):
+    async def read(self, addr):
         uvm_info(self.tag, "Doing APB read to addr " + hex(addr), UVM_HIGH)
         self.vif.PADDR.value = addr
         self.vif.PWRITE.value = 0
         self.vif.PSEL.value = 1
         await self.drive_delay()
         self.vif.PENABLE.value = 1
         await self.drive_delay()
-        data.append(self.vif.PRDATA)
+        try:
+            data = self.vif.PRDATA.value.integer
+        except TypeError or ValueError:
+            data = self.vif.PRDATA.value
         self.end_of_trans()
+        return data
 
     async def write(self, addr, data):
         uvm_info(self.tag, "Doing APB write to addr " + hex(addr), UVM_HIGH)

bus_env/bus_agent/bus_wb_driver.py

@@ -31,8 +31,9 @@ async def run_phase(self, phase):
                 await self.drive_delay()
                 self.seq_item_port.item_done()
                 continue
-            await self.send_trans(tr)
+            tr.data = await self.send_trans(tr)
             self.seq_item_port.item_done()
+            self.seq_item_port.put_response(tr)
 
     async def send_trans(self, tr):
         if tr.kind == bus_item.READ:
@@ -49,6 +50,10 @@ async def send_trans(self, tr):
         while self.vif.ack_o.value == 0:
             await self.drive_delay()
         self.end_of_trans()
+        if tr.kind == bus_item.READ:
+            return self.vif.dat_o.value.integer
+        else:
+            return tr.data
 
     def end_of_trans(self):
         self.vif.sel_i.value = 0b0000

bus_env/bus_agent/bus_wb_monitor.py

@@ -46,7 +46,7 @@ async def run_phase(self, phase):
 
     async def watch_reset(self):
         while True:
-            await FallingEdge(self.vif.rst_i)
+            await FallingEdge(self.vif.RESETn)
             # send reset tr
             tr = bus_item.type_id.create("tr", self)
             tr.kind = bus_item.RESET
@@ -70,8 +70,8 @@ async def recieve_transaction(self):
                 break
         while self.vif.ack_o.value == 0:
             await self.sample_delay()
-        address = self.adr_i.HADDR.value.integer
-        write = self.vif.HWRITE.value.integer
+        address = self.vif.adr_i.value.integer
+        write = self.vif.we_i.value.integer
         if write:
             data = self.vif.dat_i.value.integer
         else:

bus_env/bus_interface/bus_if.py

@@ -61,8 +61,8 @@ def __init__(self, dut):
 class bus_wb_if(sv_if):
     def __init__(self, dut):
         bus_map = {
-            "clk_i": "CLK",
-            "rst_i": "RESETn",
+            "CLK": "CLK",
+            "RESETn": "RESETn",
             "adr_i": "adr_i",
             "dat_i": "dat_i",
             "dat_o": "dat_o",

bus_env/bus_seq_lib/bus_seq_base.py

@@ -14,6 +14,10 @@ def __init__(self, name="bus_seq_base"):
         self.req = bus_item()
         self.rsp = bus_item()
         self.tag = name
+        # disable checking for overflow if the response queue is full
+        # if respose checking is needed the sequence should take care of it
+        self.set_response_queue_error_report_disabled(1)
+        self.response_queue_error_report_disabled = 1
 
     async def body(self):
         # get register names/address conversion dict

bus_env/bus_seq_lib/write_read_regs.py

@@ -1,4 +1,3 @@
-from uvm.seq import UVMSequence
 from uvm.macros.uvm_object_defines import uvm_object_utils
 from uvm.macros.uvm_message_defines import uvm_info, uvm_fatal
 from uvm.macros.uvm_sequence_defines import uvm_do_with, uvm_do
@@ -7,15 +6,12 @@
 from uvm.base.uvm_config_db import UVMConfigDb
 from cocotb_coverage.coverage import coverage_db
 import os
+from EF_UVM.bus_env.bus_seq_lib.bus_seq_base import bus_seq_base
 
 
-class write_read_regs(UVMSequence):
-
+class write_read_regs(bus_seq_base):
     def __init__(self, name="write_read_regs"):
-        UVMSequence.__init__(self, name)
-        self.set_automatic_phase_objection(1)
-        self.req = bus_item()
-        self.rsp = bus_item()
+        super().__init__(name)
         self.tag = name
 
     async def body(self):