relax uvm message inside the ahd driver

efabless · May 2, 2024 · b58e66c · b58e66c
1 parent 8111c02
commit b58e66c
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Showing 2 changed files with 25 additions and 6 deletions.
diff --git a/bus_env/bus_agent/bus_ahb_driver.py b/bus_env/bus_agent/bus_ahb_driver.py
@@ -19,7 +19,9 @@ async def run_phase(self, phase):
             await self.is_rising_edge()
             tr = tr[0]
             uvm_info(
-                self.tag, f"Driving trans into DUT: {tr.convert2string()} sequence id {tr.id}", UVM_LOW
+                self.tag,
+                f"Driving trans into DUT: {tr.convert2string()} sequence id {tr.id}",
+                UVM_MEDIUM,
             )
             if tr.kind == bus_item.RESET:
                 uvm_info(self.tag, "Doing reset", UVM_MEDIUM)
@@ -35,7 +37,11 @@ async def run_phase(self, phase):
                 self.seq_item_port.item_done()
 
     async def address_phase(self, tr):
-        uvm_info(self.tag, f"tr at the start of address phase {tr.convert2string()} sequence id {tr.id}", UVM_MEDIUM)
+        uvm_info(
+            self.tag,
+            f"tr at the start of address phase {tr.convert2string()} sequence id {tr.id}",
+            UVM_HIGH,
+        )
         if tr.kind == bus_item.READ:
             self.vif.HWRITE.value = 0
         else:
@@ -48,13 +54,21 @@ async def address_phase(self, tr):
         # TODO: HSIZE should be existed in the DUT wait until it got added
         await self.drive_delay()
         self.end_of_trans()
-        uvm_info(self.tag, f"tr at the end of address phase {tr.convert2string()} sequence id {tr.id}", UVM_MEDIUM)
+        uvm_info(
+            self.tag,
+            f"tr at the end of address phase {tr.convert2string()} sequence id {tr.id}",
+            UVM_HIGH,
+        )
 
     def drv_optional_signals_address(self, tr):
         pass
 
     async def data_phase(self, tr):
-        uvm_info(self.tag, f"tr at the start of data phase {tr.convert2string()} sequence id {tr.id}", UVM_MEDIUM)
+        uvm_info(
+            self.tag,
+            f"tr at the start of data phase {tr.convert2string()} sequence id {tr.id}",
+            UVM_HIGH,
+        )
         if tr.kind == bus_item.WRITE:
             self.vif.HWDATA.value = tr.data
             await self.drive_delay()
@@ -66,7 +80,11 @@ async def data_phase(self, tr):
             while self.vif.HREADYOUT == 0:
                 await self.drive_delay()
             tr.data = self.vif.HRDATA.value.integer
-        uvm_info(self.tag, f"tr at the end of data phase {tr.convert2string()} sequence id {tr.id}", UVM_MEDIUM)
+        uvm_info(
+            self.tag,
+            f"tr at the end of data phase {tr.convert2string()} sequence id {tr.id}",
+            UVM_HIGH,
+        )
         self.seq_item_port.put_response(tr)
 
     def end_of_trans(self):

diff --git a/bus_env/bus_seq_lib/bus_seq_base.py b/bus_env/bus_seq_lib/bus_seq_base.py
@@ -11,12 +11,13 @@ class bus_seq_base(UVMSequence):
     def __init__(self, name="bus_seq_base"):
         UVMSequence.__init__(self, name)
         # self.set_automatic_phase_objection(1)
-        
+
         self.tag = name
         # disable checking for overflow if the response queue is full
         # if respose checking is needed the sequence should take care of it
         self.set_response_queue_error_report_disabled(1)
         self.response_queue_error_report_disabled = 1
+
     def create_new_item(self):
         self.req = bus_item()
         self.rsp = bus_item()