continue pipe debugging

bus_env/bus_agent/bus_ahb_driver.py

@@ -19,7 +19,7 @@ async def run_phase(self, phase):
             await self.is_rising_edge()
             tr = tr[0]
             uvm_info(
-                self.tag, "Driving trans into DUT: " + tr.convert2string(), UVM_LOW
+                self.tag, f"Driving trans into DUT: {tr.convert2string()} sequence id {tr.id}", UVM_LOW
             )
             if tr.kind == bus_item.RESET:
                 uvm_info(self.tag, "Doing reset", UVM_MEDIUM)
@@ -35,6 +35,7 @@ async def run_phase(self, phase):
                 self.seq_item_port.item_done()
 
     async def address_phase(self, tr):
+        uvm_info(self.tag, f"tr at the start of address phase {tr.convert2string()} sequence id {tr.id}", UVM_MEDIUM)
         if tr.kind == bus_item.READ:
             self.vif.HWRITE.value = 0
         else:
@@ -47,11 +48,13 @@ async def address_phase(self, tr):
         # TODO: HSIZE should be existed in the DUT wait until it got added
         await self.drive_delay()
         self.end_of_trans()
+        uvm_info(self.tag, f"tr at the end of address phase {tr.convert2string()} sequence id {tr.id}", UVM_MEDIUM)
 
     def drv_optional_signals_address(self, tr):
         pass
 
     async def data_phase(self, tr):
+        uvm_info(self.tag, f"tr at the start of data phase {tr.convert2string()} sequence id {tr.id}", UVM_MEDIUM)
         if tr.kind == bus_item.WRITE:
             self.vif.HWDATA.value = tr.data
             await self.drive_delay()
@@ -63,6 +66,7 @@ async def data_phase(self, tr):
             while self.vif.HREADYOUT == 0:
                 await self.drive_delay()
             tr.data = self.vif.HRDATA.value.integer
+        uvm_info(self.tag, f"tr at the end of data phase {tr.convert2string()} sequence id {tr.id}", UVM_MEDIUM)
         self.seq_item_port.put_response(tr)
 
     def end_of_trans(self):

bus_env/bus_item.py

@@ -17,7 +17,7 @@ class bus_item(UVMSequenceItem):
     WRITE = 1
     RESET = 2
     NOPE = 3  # Insert a no-op in the sequence
-
+    counter = 0
     def __init__(self, name="bus_item"):
         super().__init__(name)
         self.tag = name
@@ -27,6 +27,8 @@ def __init__(self, name="bus_item"):
         self.rand("data", range(0, 0xFFFF))
         self.kind = bus_item.READ  # kind_e
         self.rand("kind", [bus_item.READ, bus_item.WRITE])
+        self.id = bus_item.counter
+        bus_item.counter += 1
 
     def convert2string(self):
         if self.kind == bus_item.RESET:

bus_env/bus_seq_lib/bus_seq_base.py

@@ -11,13 +11,15 @@ class bus_seq_base(UVMSequence):
     def __init__(self, name="bus_seq_base"):
         UVMSequence.__init__(self, name)
         # self.set_automatic_phase_objection(1)
-        self.req = bus_item()
-        self.rsp = bus_item()
+
         self.tag = name
         # disable checking for overflow if the response queue is full
         # if respose checking is needed the sequence should take care of it
         self.set_response_queue_error_report_disabled(1)
         self.response_queue_error_report_disabled = 1
+    def create_new_item(self):
+        self.req = bus_item()
+        self.rsp = bus_item()
 
     async def body(self):
         # get register names/address conversion dict
@@ -29,6 +31,7 @@ async def body(self):
 
     async def send_req(self, is_write, reg, data_condition=None, data_value=None):
         # send request
+        self.create_new_item()
         if data_condition is not None and data_value is not None:
             uvm_fatal(self.tag, "You should only provide data condition or data value")
         if is_write:
@@ -65,6 +68,7 @@ async def send_req(self, is_write, reg, data_condition=None, data_value=None):
         self.req.rand_mode(1)
 
     async def send_nop(self, nope_size=1):
+        self.create_new_item()
         self.req.rand_mode(0)
         self.req.addr = 0
         self.req.kind = bus_item.NOPE
@@ -73,6 +77,7 @@ async def send_nop(self, nope_size=1):
         self.req.rand_mode(1)
 
     async def send_reset(self):
+        self.create_new_item()
         self.req.rand_mode(0)
         self.req.addr = 0
         self.req.kind = bus_item.RESET