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Fixes for AHBL
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@M0stafaRady
M0stafaRady committed May 1, 2024
1 parent 03510a7 commit 114876c
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Showing 5 changed files with 50 additions and 33 deletions.
2 changes: 1 addition & 1 deletion verify/uvm-python/Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,7 @@ MODULE ?= top_module
AHB_FILES ?= $(PWD)/../../hdl/rtl/bus_wrappers/EF_SPI_AHBL.pp.v
APB_FILES ?= $(PWD)/../../hdl/rtl/bus_wrappers/EF_SPI_APB.pp.v
WB_FILES ?=$(PWD)/../../hdl/rtl/bus_wrappers/EF_SPI_WB.pp.v
HDL_FILES ?= $(PWD)/../../hdl/rtl/spi_master.v
HDL_FILES ?= $(PWD)/../../hdl/rtl/spi_master.v $(PWD)/../../hdl/rtl/EF_SPI.v
VERILOG_SOURCES ?= $(PWD)/top.v $(AHB_FILES) $(APB_FILES) $(WB_FILES) $(HDL_FILES)
RTL_MACROS += ""
BUS_TYPE ?= APB
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6 changes: 2 additions & 4 deletions verify/uvm-python/spi_ref_model/spi_ref_model.py
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Original file line number Diff line number Diff line change
Expand Up @@ -81,13 +81,11 @@ def write_bus(self, tr):
# TODO: write logic needed when read transaction is received
# For example, to read the same resgiter uncomment the following lines
data = self.regs.read_reg_value(tr.addr)
td = tr.do_clone()
if tr.addr == self.regs.reg_name_to_address["STATUS"]:
pass # don't change the data as the status register isnt calculated in the ref model for now
else:
pass
# td.data = data
self.bus_bus_export.write(td) # this is output to the scoreboard
tr.data = data
self.bus_bus_export.write(tr) # this is output to the scoreboard
self.update_interrupt_regs()

def write_ip(self, tr):
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25 changes: 16 additions & 9 deletions verify/uvm-python/spi_seq_lib/spi_MOSI_MISO_seq.py
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Original file line number Diff line number Diff line change
Expand Up @@ -54,17 +54,24 @@ async def body(self):
) # go
await self.send_nop()
await self.send_nop()
# wait until the response status is busy
while True:
await self.send_req(is_write=False, reg="STATUS")
# pop non needed response in the fifo
while True:
rsp = []
await self.get_response(rsp)
rsp = rsp[0]
uvm_info(self.get_full_name(), f"RSP: {rsp}", UVM_LOW)
if rsp.addr == self.regs.reg_name_to_address["STATUS"]:
break
if rsp.data & 0b10 == 0b0: # not busy
rsp = []
await self.get_response(rsp)
rsp = rsp[0]
uvm_info(self.get_full_name(), f"RSP: {rsp}", UVM_MEDIUM)
if rsp.addr == self.regs.reg_name_to_address["STATUS"] and rsp.data & 0b10 == 0b10: # busy
break
# wait until not busy
while True:
await self.send_nop()
await self.send_req(is_write=False, reg="STATUS")
rsp = []
await self.get_response(rsp)
rsp = rsp[0]
uvm_info(self.get_full_name(), f"RSP: {rsp} id {rsp.id}", UVM_MEDIUM)
if rsp.addr == self.regs.reg_name_to_address["STATUS"] and rsp.data & 0b10 == 0b0:
break
if random.random() > 0.3: # 70% probability of reading
await self.send_req(is_write=False, reg="DATA")
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25 changes: 15 additions & 10 deletions verify/uvm-python/spi_seq_lib/spi_send_MISO_seq.py
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Original file line number Diff line number Diff line change
Expand Up @@ -36,20 +36,25 @@ async def body(self):
is_write=True, reg="CTRL", data_condition=lambda data: data == 0b11
) # go
for _ in range(self.num_data):
# wait until the response status is busy
while True:
await self.send_req(is_write=False, reg="STATUS")
rsp = []
await self.get_response(rsp)
rsp = rsp[0]
uvm_info(self.get_full_name(), f"RSP: {rsp}", UVM_MEDIUM)
if rsp.addr == self.regs.reg_name_to_address["STATUS"] and rsp.data & 0b10 == 0b10: # busy
break
# wait until not busy
while True:
await self.send_nop()
await self.send_req(is_write=False, reg="STATUS")
# pop non needed response in the fifo
while True:
rsp = []
await self.get_response(rsp)
rsp = rsp[0]
# uvm_info(self.get_full_name(), f"RSP: {rsp}", UVM_MEDIUM)
if rsp.addr == self.regs.reg_name_to_address["STATUS"]:
break
if rsp.data & 0b10 == 0b0: # not busy
rsp = []
await self.get_response(rsp)
rsp = rsp[0]
uvm_info(self.get_full_name(), f"RSP: {rsp} id {rsp.id}", UVM_MEDIUM)
if rsp.addr == self.regs.reg_name_to_address["STATUS"] and rsp.data & 0b10 == 0b0:
break
uvm_info(self.get_full_name(), f"RSP: {rsp}", UVM_MEDIUM)

if random.random() > 0.1: # 90% probability of reading
await self.send_req(is_write=False, reg="DATA")
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25 changes: 16 additions & 9 deletions verify/uvm-python/spi_seq_lib/spi_send_MOSI_seq.py
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Original file line number Diff line number Diff line change
Expand Up @@ -40,17 +40,24 @@ async def body(self):
await self.send_req(
is_write=True, reg="CTRL", data_condition=lambda data: data == 0b11
) # go
# wait until the response status is busy
while True:
await self.send_req(is_write=False, reg="STATUS")
# pop non needed response in the fifo
while True:
rsp = []
await self.get_response(rsp)
rsp = rsp[0]
uvm_info(self.get_full_name(), f"RSP: {rsp}", UVM_MEDIUM)
if rsp.addr == self.regs.reg_name_to_address["STATUS"]:
break
if rsp.data & 0b10 == 0b0: # not busy
rsp = []
await self.get_response(rsp)
rsp = rsp[0]
uvm_info(self.get_full_name(), f"RSP: {rsp}", UVM_MEDIUM)
if rsp.addr == self.regs.reg_name_to_address["STATUS"] and rsp.data & 0b10 == 0b10: # busy
break
# wait until not busy
while True:
await self.send_nop()
await self.send_req(is_write=False, reg="STATUS")
rsp = []
await self.get_response(rsp)
rsp = rsp[0]
uvm_info(self.get_full_name(), f"RSP: {rsp} id {rsp.id}", UVM_MEDIUM)
if rsp.addr == self.regs.reg_name_to_address["STATUS"] and rsp.data & 0b10 == 0b0:
break

await self.send_req(
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