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regenerate the wrappers
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@M0stafaRady
M0stafaRady committed May 1, 2024
1 parent 66a213d commit 03510a7
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Showing 6 changed files with 30 additions and 30 deletions.
10 changes: 5 additions & 5 deletions hdl/rtl/bus_wrappers/EF_SPI_AHBL.pp.v
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Original file line number Diff line number Diff line change
Expand Up @@ -96,7 +96,7 @@

module EF_SPI_AHBL #(
parameter
CLK_DIVIDER_WIDTH = 8
CDW = 8
) (
input wire HCLK,
input wire HRESETn,
Expand Down Expand Up @@ -127,7 +127,7 @@ module EF_SPI_AHBL #(
localparam IC_REG_OFFSET = 16'd3852;

wire clk = HCLK;
wire resetb = HRESETn;
wire rst_n = HRESETn;


reg last_HSEL, last_HWRITE; reg [31:0] last_HADDR; reg [1:0] last_HTRANS;
Expand All @@ -145,7 +145,7 @@ module EF_SPI_AHBL #(

wire [1-1:0] CPOL;
wire [1-1:0] CPHA;
wire [CLK_DIVIDER_WIDTH-1:0] clk_divider;
wire [CDW-1:0] clk_divider;
wire [1-1:0] go;
wire [8-1:0] datai;
wire [8-1:0] datao;
Expand Down Expand Up @@ -215,10 +215,10 @@ module EF_SPI_AHBL #(
assign IRQ = |MIS_REG;

EF_SPI #(
.CLK_DIVIDER_WIDTH(CLK_DIVIDER_WIDTH)
.CDW(CDW)
) instance_to_wrap (
.clk(clk),
.resetb(resetb),
.rst_n(rst_n),
.CPOL(CPOL),
.CPHA(CPHA),
.clk_divider(clk_divider),
Expand Down
10 changes: 5 additions & 5 deletions hdl/rtl/bus_wrappers/EF_SPI_AHBL.v
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Original file line number Diff line number Diff line change
Expand Up @@ -28,7 +28,7 @@

module EF_SPI_AHBL #(
parameter
CLK_DIVIDER_WIDTH = 8
CDW = 8
) (
`AHBL_SLAVE_PORTS,
input [1-1:0] dout,
Expand All @@ -48,14 +48,14 @@ module EF_SPI_AHBL #(
localparam IC_REG_OFFSET = `AHBL_AW'd3852;

wire clk = HCLK;
wire resetb = HRESETn;
wire rst_n = HRESETn;


`AHBL_CTRL_SIGNALS

wire [1-1:0] CPOL;
wire [1-1:0] CPHA;
wire [CLK_DIVIDER_WIDTH-1:0] clk_divider;
wire [CDW-1:0] clk_divider;
wire [1-1:0] go;
wire [8-1:0] datai;
wire [8-1:0] datao;
Expand Down Expand Up @@ -110,10 +110,10 @@ module EF_SPI_AHBL #(
assign IRQ = |MIS_REG;

EF_SPI #(
.CLK_DIVIDER_WIDTH(CLK_DIVIDER_WIDTH)
.CDW(CDW)
) instance_to_wrap (
.clk(clk),
.resetb(resetb),
.rst_n(rst_n),
.CPOL(CPOL),
.CPHA(CPHA),
.clk_divider(clk_divider),
Expand Down
10 changes: 5 additions & 5 deletions hdl/rtl/bus_wrappers/EF_SPI_APB.pp.v
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Original file line number Diff line number Diff line change
Expand Up @@ -85,7 +85,7 @@

module EF_SPI_APB #(
parameter
CLK_DIVIDER_WIDTH = 8
CDW = 8
) (
input wire PCLK,
input wire PRESETn,
Expand Down Expand Up @@ -115,7 +115,7 @@ module EF_SPI_APB #(
localparam IC_REG_OFFSET = 16'd3852;

wire clk = PCLK;
wire resetb = PRESETn;
wire rst_n = PRESETn;


wire apb_valid = PSEL & PENABLE;
Expand All @@ -124,7 +124,7 @@ module EF_SPI_APB #(

wire [1-1:0] CPOL;
wire [1-1:0] CPHA;
wire [CLK_DIVIDER_WIDTH-1:0] clk_divider;
wire [CDW-1:0] clk_divider;
wire [1-1:0] go;
wire [8-1:0] datai;
wire [8-1:0] datao;
Expand Down Expand Up @@ -195,10 +195,10 @@ module EF_SPI_APB #(
assign IRQ = |MIS_REG;

EF_SPI #(
.CLK_DIVIDER_WIDTH(CLK_DIVIDER_WIDTH)
.CDW(CDW)
) instance_to_wrap (
.clk(clk),
.resetb(resetb),
.rst_n(rst_n),
.CPOL(CPOL),
.CPHA(CPHA),
.clk_divider(clk_divider),
Expand Down
10 changes: 5 additions & 5 deletions hdl/rtl/bus_wrappers/EF_SPI_APB.v
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Original file line number Diff line number Diff line change
Expand Up @@ -28,7 +28,7 @@

module EF_SPI_APB #(
parameter
CLK_DIVIDER_WIDTH = 8
CDW = 8
) (
`APB_SLAVE_PORTS,
input [1-1:0] dout,
Expand All @@ -48,14 +48,14 @@ module EF_SPI_APB #(
localparam IC_REG_OFFSET = `APB_AW'd3852;

wire clk = PCLK;
wire resetb = PRESETn;
wire rst_n = PRESETn;


`APB_CTRL_SIGNALS

wire [1-1:0] CPOL;
wire [1-1:0] CPHA;
wire [CLK_DIVIDER_WIDTH-1:0] clk_divider;
wire [CDW-1:0] clk_divider;
wire [1-1:0] go;
wire [8-1:0] datai;
wire [8-1:0] datao;
Expand Down Expand Up @@ -110,10 +110,10 @@ module EF_SPI_APB #(
assign IRQ = |MIS_REG;

EF_SPI #(
.CLK_DIVIDER_WIDTH(CLK_DIVIDER_WIDTH)
.CDW(CDW)
) instance_to_wrap (
.clk(clk),
.resetb(resetb),
.rst_n(rst_n),
.CPOL(CPOL),
.CPHA(CPHA),
.clk_divider(clk_divider),
Expand Down
10 changes: 5 additions & 5 deletions hdl/rtl/bus_wrappers/EF_SPI_WB.pp.v
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Original file line number Diff line number Diff line change
Expand Up @@ -78,7 +78,7 @@

module EF_SPI_WB #(
parameter
CLK_DIVIDER_WIDTH = 8
CDW = 8
) (
input wire ext_clk,
input wire clk_i,
Expand Down Expand Up @@ -109,7 +109,7 @@ module EF_SPI_WB #(
localparam IC_REG_OFFSET = 16'd3852;

wire clk = clk_i;
wire resetb = (~rst_i);
wire rst_n = (~rst_i);


wire wb_valid = cyc_i & stb_i;
Expand All @@ -119,7 +119,7 @@ module EF_SPI_WB #(

wire [1-1:0] CPOL;
wire [1-1:0] CPHA;
wire [CLK_DIVIDER_WIDTH-1:0] clk_divider;
wire [CDW-1:0] clk_divider;
wire [1-1:0] go;
wire [8-1:0] datai;
wire [8-1:0] datao;
Expand Down Expand Up @@ -178,10 +178,10 @@ module EF_SPI_WB #(
assign IRQ = |MIS_REG;

EF_SPI #(
.CLK_DIVIDER_WIDTH(CLK_DIVIDER_WIDTH)
.CDW(CDW)
) instance_to_wrap (
.clk(clk),
.resetb(resetb),
.rst_n(rst_n),
.CPOL(CPOL),
.CPHA(CPHA),
.clk_divider(clk_divider),
Expand Down
10 changes: 5 additions & 5 deletions hdl/rtl/bus_wrappers/EF_SPI_WB.v
View file
Original file line number Diff line number Diff line change
Expand Up @@ -28,7 +28,7 @@

module EF_SPI_WB #(
parameter
CLK_DIVIDER_WIDTH = 8
CDW = 8
) (
`WB_SLAVE_PORTS,
input [1-1:0] dout,
Expand All @@ -48,14 +48,14 @@ module EF_SPI_WB #(
localparam IC_REG_OFFSET = `WB_AW'd3852;

wire clk = clk_i;
wire resetb = (~rst_i);
wire rst_n = (~rst_i);


`WB_CTRL_SIGNALS

wire [1-1:0] CPOL;
wire [1-1:0] CPHA;
wire [CLK_DIVIDER_WIDTH-1:0] clk_divider;
wire [CDW-1:0] clk_divider;
wire [1-1:0] go;
wire [8-1:0] datai;
wire [8-1:0] datao;
Expand Down Expand Up @@ -110,10 +110,10 @@ module EF_SPI_WB #(
assign IRQ = |MIS_REG;

EF_SPI #(
.CLK_DIVIDER_WIDTH(CLK_DIVIDER_WIDTH)
.CDW(CDW)
) instance_to_wrap (
.clk(clk),
.resetb(resetb),
.rst_n(rst_n),
.CPOL(CPOL),
.CPHA(CPHA),
.clk_divider(clk_divider),
Expand Down

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