Test signal generator wiring and firmware

.gitignore

@@ -0,0 +1,98 @@
+# Logs
+logs
+*.log
+npm-debug.log*
+
+# Runtime data
+pids
+*.pid
+*.seed
+
+# Directory for instrumented libs generated by jscoverage/JSCover
+lib-cov
+
+# Coverage directory used by tools like istanbul
+coverage
+
+# Grunt intermediate storage (http://gruntjs.com/creating-plugins#storing-task-files)
+.grunt
+
+# node-waf configuration
+.lock-wscript
+
+# Compiled binary addons (http://nodejs.org/api/addons.html)
+build/Release
+
+# Dependency directories
+node_modules
+jspm_packages
+
+# Optional npm cache directory
+.npm
+
+# Optional REPL history
+.node_repl_history
+
+# =========================
+# Operating System Files
+# =========================
+
+# OSX
+# =========================
+
+.DS_Store
+.AppleDouble
+.LSOverride
+
+# Thumbnails
+._*
+
+# Files that might appear in the root of a volume
+.DocumentRevisions-V100
+.fseventsd
+.Spotlight-V100
+.TemporaryItems
+.Trashes
+.VolumeIcon.icns
+
+# Directories potentially created on remote AFP share
+.AppleDB
+.AppleDesktop
+Network Trash Folder
+Temporary Items
+.apdisk
+
+# Windows
+# =========================
+
+# Windows image file caches
+Thumbs.db
+ehthumbs.db
+
+# Folder config file
+Desktop.ini
+
+# Recycle Bin used on file shares
+$RECYCLE.BIN/
+
+# Windows Installer files
+*.cab
+*.msi
+*.msm
+*.msp
+
+# Windows shortcuts
+*.lnk
+
+# Quartus II intermediate files
+*/db
+*/*/db
+*/.qsys_edit
+*/devkits
+*/greybox_tmp
+*/*/incremental_db
+*/incremental_db
+*/*/output_files
+*/output_files
+*/*/output_file.map
+

testcircuit/README.md

@@ -4,20 +4,23 @@ In case of a series production of the mod, you probably need some means
 to test the mod boards without actually installing them into a real C64.
 For this purpose, the necessary input signals can be generated by a 
 second FPGA board, programmed to simulate the various VIC signals.
+These are fed into the VIC adapter board (via a ZIF socket for example)
+which will in turn drive the FPGA board to generate the test image.
 
 The provided firmware will turn a standard C64 video enhanchement board 
 to a signal generator that uses the GPIO1 port and two additional pins for output
 instead of input.
 Be careful to use such a board only for this test purpose, as
 it will cause damage to connect some other signal source to these outputs.
 
+![alt text](breadboard.jpg "Experimental setup using a breadboard")	
 
 ## Wiring the power 
 
 | Power input  | Signal generator | VIC adapter |
 | ------------ | ---------------- | ----------- |
 | +5V          | RFCONC2 1        | Pin 40      |
-| GND          | RFCONC2 3        | Pin 20      |
+| GND          | SW1 3            | Pin 20      |
 
 ## Wiring up the signal generator outputs to the VIC adapter
 
@@ -46,3 +49,10 @@ it will cause damage to connect some other signal source to these outputs.
 | 75       | GPIO1 2          | Pin 37       | DB9         |
 | 39       | SW1 1            | Pin 38       | DB8         |
 | 40       | SW1 2            | Pin 39       | DB7         |
+
+## Firmware
+
+The signal generator board needs a dedicated firmware that turns 
+a standard C64 video enhancement board a signal generator for testing.
+This file is called TestSignalGenerator.pof and can be found 
+right in this folder.

testcircuit/quartus/PLL_7_882.cmp

@@ -0,0 +1,22 @@
+--Copyright (C) 2018  Intel Corporation. All rights reserved.
+--Your use of Intel Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Intel Program License 
+--Subscription Agreement, the Intel Quartus Prime License Agreement,
+--the Intel FPGA IP License Agreement, or other applicable license
+--agreement, including, without limitation, that your use is for
+--the sole purpose of programming logic devices manufactured by
+--Intel and sold by Intel or its authorized distributors.  Please
+--refer to the applicable agreement for further details.
+
+
+component PLL_7_882
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC 
+	);
+end component;

testcircuit/quartus/PLL_7_882.ppf

@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="MAX 10" variation_name="PLL_7_882" megafunction_name="ALTPLL" specifies="all_ports">
+<global>
+<pin name="inclk0" direction="input" scope="external" source="clock"  />
+<pin name="c0" direction="output" scope="external" source="clock"  />
+
+</global>
+</pinplan>

testcircuit/quartus/PLL_7_882.qip

@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "18.1"
+set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "PLL_7_882.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "PLL_7_882.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "PLL_7_882.ppf"]