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antmicro / verilator Public

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WIP: Sum coverage counts of variables in parameterized modules #4655

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WIP: Sum coverage counts of variables in parameterized modules

WIP: Sum coverage counts of variables in parameterized modules #4655

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1 error

Process completed with exit code 2.

Test | ubuntu-24.04 | gcc | dist-vlt-3

Test | ubuntu-24.04 | gcc | dist-vlt-3

failed Jan 9, 2025 in 11m 13s

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