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antmicro / verilator Public

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WIP: Sum coverage counts of variables in parameterized modules #4655

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WIP: Sum coverage counts of variables in parameterized modules

WIP: Sum coverage counts of variables in parameterized modules #4655

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1 error

Process completed with exit code 2.

Test | ubuntu-20.04 | gcc-10 | reloc | dist-vlt-1

Test | ubuntu-20.04 | gcc-10 | reloc | dist-vlt-1

failed Jan 9, 2025 in 9m 4s

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