😎 Decrypt & Decrypt Round (#7)

* 😎 Decrypt & Decrypt Round * 💄 Code Styling --------- Co-authored-by: AhmedSobhy01 <[email protected]>
AhmedSobhy01 · Apr 22, 2024 · 2e02d9f · 2e02d9f
1 parent f51c247
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Showing 4 changed files with 102 additions and 26 deletions.
diff --git a/AESDecrypt.v b/AESDecrypt.v
@@ -0,0 +1,57 @@
+module AESDecrypt #(parameter Nk = 4,parameter Nr = 10) (data, key, out, clk);
+	input [127:0] data;
+	input [Nk * 32 - 1:0] key;
+	input clk;
+	output [127:0] out;
+
+	reg [127:0] state;
+	reg [127:0] keyReg; 
+	reg [3:0] roundCount = 0;
+	wire [127:0] stateAfterLastRound;
+	wire [127:0] stateAfterKey;
+	wire [127:0] stateAfterRound;
+
+	wire [(11 * 128) - 1:0] allKeys;
+
+	KeyExpansion keysGetter( key , allKeys);
+	AddRoundKey a(state, keyReg , stateAfterKey);
+	DecryptRound round(state , keyReg , stateAfterRound);
+	LastDecryptRound lastRound (state , keyReg , stateAfterLastRound);
+
+	assign out = state;
+
+	always @(posedge clk) begin
+		if (roundCount == 0)begin
+			keyReg = allKeys [((11 * 128) - 1) -: 128 ] ;
+			state = data;
+		end
+		else if (roundCount == 1)
+			state <= stateAfterKey;
+		else if (roundCount < Nr +1)
+			state <= stateAfterRound;
+		else if (roundCount == Nr +1)
+			state <= stateAfterLastRound;
+
+		if (roundCount > 0 && roundCount < Nr + 1)
+			keyReg <= allKeys [((11 * 128) - roundCount * 128 - 1) -: 128 ];	
+
+		if (roundCount < Nr + 2)
+			roundCount <= roundCount + 1;
+	end
+endmodule
+
+module AESDecrypt_DUT();
+	reg [127:0] data;
+	reg [127:0] key;
+	wire [127:0] out;
+	reg clk;
+
+	AESDecrypt aes(data,key,out,clk);
+
+	initial begin
+		key = 128'h000102030405060708090a0b0c0d0e0f;
+		data = 128'h69c4e0d86a7b0430d8cdb78070b4c55a;
+		clk = 0;
+		forever #10 clk = ~clk;
+	end
+endmodule
diff --git a/AESEncrypt.v b/AESEncrypt.v
@@ -1,10 +1,11 @@
 
-module AESEncrypt #(parameter Nk = 4,parameter Nr = 10) (data,key,out,clk);
+module AESEncrypt #(parameter Nk = 4,parameter Nr = 10) (data, key, out, clk);
 	input [127:0] data;
 	input [Nk * 32 - 1:0] key;
 	input clk;
 	output [127:0] out;
-	reg [127:0]state;
+
+	reg [127:0] state;
 	reg [127:0] keyReg;
 	reg [3:0] roundCount = 0;
 	wire [127:0] stateAfterLastRound;
@@ -17,31 +18,28 @@ module AESEncrypt #(parameter Nk = 4,parameter Nr = 10) (data,key,out,clk);
 	EncryptRound round(state,keyReg,stateAfterRound);
 	LastEncryptRound lastRound(state,keyReg,stateAfterLastRound);
 
-
 	assign out = state;
 
 	always @(posedge clk) begin
-		if(roundCount == 0)begin
+		if (roundCount == 0) begin
 			keyReg = key;
 			state = data;
 		end
-		else if(roundCount == 1)
+		else if (roundCount == 1)
 			state <= stateAfterKey;
 		else if (roundCount < Nr +1)
 			state <= stateAfterRound;
-		else if(roundCount == Nr +1)
+		else if (roundCount == Nr +1)
 			state <= stateAfterLastRound;
 
-		if(roundCount > 0 && roundCount < Nr + 1)
+		if (roundCount > 0 && roundCount < Nr + 1)
 			keyReg <= keyWire;	
 
-		if(roundCount < Nr + 2)
+		if (roundCount < Nr + 2)
 			roundCount <= roundCount + 1;
 	end
-
 endmodule
 
-
 module AESEncrypt_DUT();
 	reg [127:0] data;
 	reg [127:0] key;
@@ -56,6 +54,4 @@ module AESEncrypt_DUT();
 		clk = 0;
 		forever #10 clk = ~clk;
 	end
-endmodule
-
-
+endmodule
diff --git a/DecryptRound.v b/DecryptRound.v
@@ -0,0 +1,27 @@
+module DecryptRound(stateIn, key, stateOut);
+	input [127:0] stateIn;
+	input [127:0] key;
+	output [127:0] stateOut;
+
+	wire [127:0] subByteWire;
+	wire [127:0] shiftRowsWire;
+	wire [127:0] afterRoundKey;
+
+	InvShiftRows shft(stateIn, shiftRowsWire);	
+	InvSubBytes sub(shiftRowsWire, subByteWire);
+	AddRoundKey addkey(subByteWire, key, afterRoundKey);
+	InvMixColumns mix(afterRoundKey, stateOut);	
+endmodule 
+
+module LastDecryptRound(stateIn, key, stateOut);
+	input [127:0] stateIn;
+	input [127:0] key;
+	output [127:0] stateOut;
+
+	wire [127:0] subByteWire;
+	wire [127:0] shiftRowsWire;
+
+	InvShiftRows shft(stateIn, shiftRowsWire);	
+	InvSubBytes sub(shiftRowsWire, subByteWire);
+	AddRoundKey addkey(subByteWire, key, stateOut);
+endmodule 
diff --git a/EncryptRound.v b/EncryptRound.v
@@ -1,4 +1,4 @@
-module EncryptRound(stateIn,key,stateOut);
+module EncryptRound(stateIn, key, stateOut);
 	input [127:0] stateIn;
 	input [127:0] key;
 	output [127:0] stateOut;
@@ -7,25 +7,21 @@ module EncryptRound(stateIn,key,stateOut);
 	wire [127:0] shiftRowsWire;
 	wire [127:0] mixColumnsWire;
 
-	SubBytes sub(stateIn,subByteWire);
-	ShiftRows shft(subByteWire,shiftRowsWire);	
-	MixColumns mix(shiftRowsWire,mixColumnsWire);	
-	AddRoundKey addkey(mixColumnsWire,key,stateOut);
-
+	SubBytes sub(stateIn, subByteWire);
+	ShiftRows shft(subByteWire, shiftRowsWire);	
+	MixColumns mix(shiftRowsWire, mixColumnsWire);	
+	AddRoundKey addkey(mixColumnsWire, key, stateOut);
 endmodule 
 
-
-
-module LastEncryptRound(stateIn,key,stateOut);
+module LastEncryptRound(stateIn, key, stateOut);
 	input [127:0] stateIn;
 	input [127:0] key;
 	output [127:0] stateOut;
 
 	wire [127:0] subByteWire;
 	wire [127:0] shiftRowsWire;
 
-	SubBytes sub(stateIn,subByteWire);
-	ShiftRows shft(subByteWire,shiftRowsWire);	
-	AddRoundKey addkey(shiftRowsWire,key,stateOut);
-
+	SubBytes sub(stateIn, subByteWire);
+	ShiftRows shft(subByteWire, shiftRowsWire);	
+	AddRoundKey addkey(shiftRowsWire, key, stateOut);
 endmodule