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✨ Main module (#6)
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* round module done

* main module sorta done

* fixed a typo

* Encryption working yay

* Delete AESEncrypt.v.bak

* removed unneeded extra sbox

* 📝 Changed MixColumns filename

* 🔥 Removed DecryptRound duplicate code

* 📝 Changed module name in AESENncrypt_DUT

---------

Co-authored-by: AhmedSobhy01 <[email protected]>
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@AhmedAmrNabil @AhmedSobhy01
AhmedAmrNabil and AhmedSobhy01 authored Apr 22, 2024
1 parent 959d8c3 commit f51c247
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1 change: 1 addition & 0 deletions .gitignore
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testing/
61 changes: 61 additions & 0 deletions AESEncrypt.v
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module AESEncrypt #(parameter Nk = 4,parameter Nr = 10) (data,key,out,clk);
input [127:0] data;
input [Nk * 32 - 1:0] key;
input clk;
output [127:0] out;
reg [127:0]state;
reg [127:0] keyReg;
reg [3:0] roundCount = 0;
wire [127:0] stateAfterLastRound;
wire [127:0] stateAfterKey;
wire [127:0] stateAfterRound;
wire [127:0] keyWire;

KeyExpansionRound keyexpround(roundCount,keyReg,keyWire);
AddRoundKey a(state,keyReg,stateAfterKey);
EncryptRound round(state,keyReg,stateAfterRound);
LastEncryptRound lastRound(state,keyReg,stateAfterLastRound);


assign out = state;

always @(posedge clk) begin
if(roundCount == 0)begin
keyReg = key;
state = data;
end
else if(roundCount == 1)
state <= stateAfterKey;
else if (roundCount < Nr +1)
state <= stateAfterRound;
else if(roundCount == Nr +1)
state <= stateAfterLastRound;

if(roundCount > 0 && roundCount < Nr + 1)
keyReg <= keyWire;

if(roundCount < Nr + 2)
roundCount <= roundCount + 1;
end

endmodule


module AESEncrypt_DUT();
reg [127:0] data;
reg [127:0] key;
wire [127:0] out;
reg clk;

AESEncrypt aes(data,key,out,clk);

initial begin
key = 128'h000102030405060708090a0b0c0d0e0f;
data = 128'h00112233445566778899aabbccddeeff;
clk = 0;
forever #10 clk = ~clk;
end
endmodule


14 changes: 7 additions & 7 deletions AddRoundKey.v
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module AddRoundKey(state, roundKey, newRoundKey);
module AddRoundKey(state, roundKey, stateOut);
input [127:0] state, roundKey;
output [127:0] newRoundKey;
output [127:0] stateOut;

assign newRoundKey= state ^ roundKey;
assign stateOut= state ^ roundKey;
endmodule

module AddRoundKey_DUT();
reg [127:0] state, roundKey;
wire [127:0] newRoundKey;
wire [127:0] stateOut;

AddRoundKey ark(state, roundKey, newRoundKey);
AddRoundKey ark(state, roundKey, stateOut);

initial begin
state = 128'h_046681e5_e0cb199a_48f8d37a_2806264c;
roundKey = 128'h_a0fafe17_88542cb1_23a33939_2a6c7605;
#10
state = newRoundKey;
state = stateOut;
roundKey = 128'h_a0fafe17_88542cb1_23a33939_2a6c7605;
end

initial begin
$display("AddRoundKey_DUT");
$display("==================================");
$monitor("State = %h, Key = %h, New Key= %h", state, roundKey, newRoundKey);
$monitor("State = %h, Key = %h, New Key= %h", state, roundKey, stateOut);
end
endmodule
Empty file added DecryptRound.v
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31 changes: 31 additions & 0 deletions EncryptRound.v
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module EncryptRound(stateIn,key,stateOut);
input [127:0] stateIn;
input [127:0] key;
output [127:0] stateOut;

wire [127:0] subByteWire;
wire [127:0] shiftRowsWire;
wire [127:0] mixColumnsWire;

SubBytes sub(stateIn,subByteWire);
ShiftRows shft(subByteWire,shiftRowsWire);
MixColumns mix(shiftRowsWire,mixColumnsWire);
AddRoundKey addkey(mixColumnsWire,key,stateOut);

endmodule



module LastEncryptRound(stateIn,key,stateOut);
input [127:0] stateIn;
input [127:0] key;
output [127:0] stateOut;

wire [127:0] subByteWire;
wire [127:0] shiftRowsWire;

SubBytes sub(stateIn,subByteWire);
ShiftRows shft(subByteWire,shiftRowsWire);
AddRoundKey addkey(shiftRowsWire,key,stateOut);

endmodule
2 changes: 1 addition & 1 deletion KeyExpansion.v
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Expand Up @@ -23,7 +23,7 @@ module KeyExpansionRound(roundCount, keyIn, keyOut);

generate
for (i = 0; i < 4; i = i + 1) begin: SBoxLoop
SBox sBox(w3Rot[i * 8 +: 8], w3Sub[i * 8 +: 8]);
SubTable sBox(w3Rot[i * 8 +: 8], w3Sub[i * 8 +: 8]);
end
endgenerate

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106 changes: 53 additions & 53 deletions mixColumns.v → MixColumns.v
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module MixColumns(stateIn, stateOut);
input [127:0] stateIn;
output [127:0] stateOut;

// Function to multiply by 2 and fix the overflow
function [7:0] xtime;
input [7:0] in;
if(in[7] == 1) xtime = (in << 1) ^ 8'h1B;
else xtime = in << 1;
endfunction

genvar i;
generate
for(i = 0; i < 4; i = i + 1)begin: mixColumnsLoop
// state[0,c] = 2*state[0,c] + (2 * state[1,c] + state[1,c]) + state[2,c] + state[3,c]
assign stateOut[32*i+24+:8] = xtime(stateIn[32*i+24+:8]) ^ (xtime(stateIn[32*i+16+:8]) ^ stateIn[32*i+16+:8]) ^ stateIn[32*i+8 +:8] ^ stateIn[32*i +:8];

// state[1,c] = 2*state[1,c] + (2 * state[2,c] + state[2,c]) + state[3,c] + state[0,c]
assign stateOut[32*i+16+:8] = xtime(stateIn[32*i+16+:8]) ^ (xtime(stateIn[32*i+8 +:8]) ^ stateIn[32*i+8 +:8]) ^ stateIn[32*i +:8] ^ stateIn[32*i+24+:8];

// state[2,c] = 2*state[2,c] + (2 * state[3,c] + state[3,c]) + state[0,c] + state[1,c]
assign stateOut[32*i+8 +:8] = xtime(stateIn[32*i+8 +:8]) ^ (xtime(stateIn[32*i +:8]) ^ stateIn[32*i +:8]) ^ stateIn[32*i+24+:8] ^ stateIn[32*i+16+:8];

// state[3,c] = 2*state[3,c] + (2 * state[0,c] + state[0,c]) + state[1,c] + state[2,c]
assign stateOut[32*i +:8] = xtime(stateIn[32*i +:8]) ^ (xtime(stateIn[32*i+24+:8]) ^ stateIn[32*i+24+:8]) ^ stateIn[32*i+16+:8] ^ stateIn[32*i+8 +:8];
end
endgenerate
endmodule

module MixColumns_DUT();
reg [127:0] stateIn;
wire [127:0] stateOut;

MixColumns mc(stateIn, stateOut);

initial begin
stateIn = 128'h6353e08c0960e104cd70b751bacad0e7;
#10
stateIn = 128'h84e1dd691a41d76f792d389783fbac70;
#10
stateIn = 128'h1fb5430ef0accf64aa370cde3d77792c;
end

initial begin
$display("MixColumns_DUT");
$display("==================================");
$monitor("Expected: 5f72641557f5bc92f7be3b291db9f91a, Actual: %h\n",stateOut);
#10
$monitor("Expected: 9f487f794f955f662afc86abd7f1ab29, Actual: %h\n",stateOut);
#10
$monitor("Expected: b7a53ecbbf9d75a0c40efc79b674cc11, Actual: %h\n",stateOut);
end

module MixColumns(stateIn, stateOut);
input [127:0] stateIn;
output [127:0] stateOut;

// Function to multiply by 2 and fix the overflow
function [7:0] xtime;
input [7:0] in;
if(in[7] == 1) xtime = (in << 1) ^ 8'h1B;
else xtime = in << 1;
endfunction

genvar i;
generate
for(i = 0; i < 4; i = i + 1)begin: mixColumnsLoop
// state[0,c] = 2*state[0,c] + (2 * state[1,c] + state[1,c]) + state[2,c] + state[3,c]
assign stateOut[32*i+24+:8] = xtime(stateIn[32*i+24+:8]) ^ (xtime(stateIn[32*i+16+:8]) ^ stateIn[32*i+16+:8]) ^ stateIn[32*i+8 +:8] ^ stateIn[32*i +:8];

// state[1,c] = 2*state[1,c] + (2 * state[2,c] + state[2,c]) + state[3,c] + state[0,c]
assign stateOut[32*i+16+:8] = xtime(stateIn[32*i+16+:8]) ^ (xtime(stateIn[32*i+8 +:8]) ^ stateIn[32*i+8 +:8]) ^ stateIn[32*i +:8] ^ stateIn[32*i+24+:8];

// state[2,c] = 2*state[2,c] + (2 * state[3,c] + state[3,c]) + state[0,c] + state[1,c]
assign stateOut[32*i+8 +:8] = xtime(stateIn[32*i+8 +:8]) ^ (xtime(stateIn[32*i +:8]) ^ stateIn[32*i +:8]) ^ stateIn[32*i+24+:8] ^ stateIn[32*i+16+:8];

// state[3,c] = 2*state[3,c] + (2 * state[0,c] + state[0,c]) + state[1,c] + state[2,c]
assign stateOut[32*i +:8] = xtime(stateIn[32*i +:8]) ^ (xtime(stateIn[32*i+24+:8]) ^ stateIn[32*i+24+:8]) ^ stateIn[32*i+16+:8] ^ stateIn[32*i+8 +:8];
end
endgenerate
endmodule

module MixColumns_DUT();
reg [127:0] stateIn;
wire [127:0] stateOut;

MixColumns mc(stateIn, stateOut);

initial begin
stateIn = 128'h6353e08c0960e104cd70b751bacad0e7;
#10
stateIn = 128'h84e1dd691a41d76f792d389783fbac70;
#10
stateIn = 128'h1fb5430ef0accf64aa370cde3d77792c;
end

initial begin
$display("MixColumns_DUT");
$display("==================================");
$monitor("Expected: 5f72641557f5bc92f7be3b291db9f91a, Actual: %h\n",stateOut);
#10
$monitor("Expected: 9f487f794f955f662afc86abd7f1ab29, Actual: %h\n",stateOut);
#10
$monitor("Expected: b7a53ecbbf9d75a0c40efc79b674cc11, Actual: %h\n",stateOut);
end
endmodule
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