Merge remote-tracking branch 'remotes/origin/master' into for-yarc

Signed-off-by: yqszxx <[email protected]>

# Conflicts:
#	instruction/addiw.go
#	instruction/addw.go
#	instruction/csrrc.go
#	instruction/csrrci.go
#	instruction/csrrs.go
#	instruction/csrrsi.go
#	instruction/csrrw.go
#	instruction/csrrwi.go
#	instruction/ecall.go
#	instruction/fence.go
#	instruction/fence_i.go
#	instruction/ld.go
#	instruction/lwu.go
#	instruction/mret.go
#	instruction/sd.go
#	instruction/slliw.go
#	instruction/sllw.go
#	instruction/sraiw.go
#	instruction/sraw.go
#	instruction/sret.go
#	instruction/srliw.go
#	instruction/srlw.go
#	instruction/subw.go
#	main.go
#	mem/mem.go
#	processor/processor.go
#	reg/csr.go

instruction/add.go

@@ -1,8 +1,8 @@
 package instruction
 
 import (
+	"github.com/yqszxx/yars/bv"
 	"log"
-	"yars/bv"
 )
 
 // ADD performs addition. Overflow is ignored and the low 64 bits of results are written to the

instruction/addi.go

@@ -1,8 +1,8 @@
 package instruction
 
 import (
+	"github.com/yqszxx/yars/bv"
 	"log"
-	"yars/bv"
 )
 
 // ADDI adds the sign-extended 12-bit immediate to register rs1. Arithmetic overflow is ignored and

instruction/and.go

@@ -1,8 +1,8 @@
 package instruction
 
 import (
+	"github.com/yqszxx/yars/bv"
 	"log"
-	"yars/bv"
 )
 
 // AND performs bitwise AND logical operation.

instruction/andi.go

@@ -1,8 +1,8 @@
 package instruction
 
 import (
+	"github.com/yqszxx/yars/bv"
 	"log"
-	"yars/bv"
 )
 
 // ANDI is a logical operation that performs bitwise AND on register rs1 and the sign-extended

instruction/auipc.go

@@ -1,8 +1,8 @@
 package instruction
 
 import (
+	"github.com/yqszxx/yars/bv"
 	"log"
-	"yars/bv"
 )
 
 // AUIPC (add upper immediate to pc) appends 12 low-order zero bits to the 20-bit U-immediate,

instruction/beq.go

@@ -1,8 +1,8 @@
 package instruction
 
 import (
+	"github.com/yqszxx/yars/bv"
 	"log"
-	"yars/bv"
 )
 
 // BEQ branch instruction compares two registers. It takes the branch if registers rs1 and rs2 are equal.

instruction/bge.go

@@ -1,8 +1,8 @@
 package instruction
 
 import (
+	"github.com/yqszxx/yars/bv"
 	"log"
-	"yars/bv"
 )
 
 // BGE branch instruction compares two registers. It takes the branch if rs1 is greater than or equal

instruction/bgeu.go

@@ -1,8 +1,8 @@
 package instruction
 
 import (
+	"github.com/yqszxx/yars/bv"
 	"log"
-	"yars/bv"
 )
 
 // BGEU branch instruction compares two registers. It takes the branch if rs1 is greater than or equal

instruction/blt.go

@@ -1,8 +1,8 @@
 package instruction
 
 import (
+	"github.com/yqszxx/yars/bv"
 	"log"
-	"yars/bv"
 )
 
 // BLT branch instruction compares two registers. It takes the branch if rs1 is less than rs2, using

instruction/bltu.go

@@ -1,8 +1,8 @@
 package instruction
 
 import (
+	"github.com/yqszxx/yars/bv"
 	"log"
-	"yars/bv"
 )
 
 // BLTU branch instruction compares two registers. It takes the branch if rs1 is less than rs2, using

instruction/bne.go

@@ -1,8 +1,8 @@
 package instruction
 
 import (
+	"github.com/yqszxx/yars/bv"
 	"log"
-	"yars/bv"
 )
 
 // BNE branch instruction compares two registers. It takes the branch if registers rs1 and rs2 are unequal.

instruction/instruction.go

@@ -1,8 +1,8 @@
 package instruction
 
 import (
-	"yars/bv"
-	"yars/intf"
+	"github.com/yqszxx/yars/bv"
+	"github.com/yqszxx/yars/intf"
 )
 
 type Instruction struct {

instruction/jal.go

@@ -1,8 +1,8 @@
 package instruction
 
 import (
+	"github.com/yqszxx/yars/bv"
 	"log"
-	"yars/bv"
 )
 
 // JAL (jump and link) uses the J-type format, where the J-immediate encodes a signed offset

instruction/jalr.go

@@ -1,8 +1,8 @@
 package instruction
 
 import (
+	"github.com/yqszxx/yars/bv"
 	"log"
-	"yars/bv"
 )
 
 // JALR (jump and link register) uses the I-type encoding. The target address is obtained

instruction/lb.go

@@ -1,9 +1,9 @@
 package instruction
 
 import (
+	"github.com/yqszxx/yars/bv"
+	"github.com/yqszxx/yars/intf"
 	"log"
-	"yars/bv"
-	"yars/intf"
 )
 
 // LB loads a 8-bit value from memory, then sign-extends to 32-bits before storing in rd.

instruction/lbu.go

@@ -1,9 +1,9 @@
 package instruction
 
 import (
+	"github.com/yqszxx/yars/bv"
+	"github.com/yqszxx/yars/intf"
 	"log"
-	"yars/bv"
-	"yars/intf"
 )
 
 // LB loads a 8-bit value from memory, then zero-extends to 32-bits before storing in rd.

instruction/lh.go

@@ -1,9 +1,9 @@
 package instruction
 
 import (
+	"github.com/yqszxx/yars/bv"
+	"github.com/yqszxx/yars/intf"
 	"log"
-	"yars/bv"
-	"yars/intf"
 )
 
 // LH loads a 16-bit value from memory, then sign-extends to 32-bits before storing in rd.

instruction/lhu.go

@@ -1,9 +1,9 @@
 package instruction
 
 import (
+	"github.com/yqszxx/yars/bv"
+	"github.com/yqszxx/yars/intf"
 	"log"
-	"yars/bv"
-	"yars/intf"
 )
 
 // LHU loads a 16-bit value from memory, then zero-extends to 32-bits before storing in rd.

instruction/lui.go

@@ -1,8 +1,8 @@
 package instruction
 
 import (
+	"github.com/yqszxx/yars/bv"
 	"log"
-	"yars/bv"
 )
 
 // LUI (load upper immediate) places the 20-bit U-immediate into bits 31–12 of register

instruction/lw.go

@@ -1,9 +1,9 @@
 package instruction
 
 import (
+	"github.com/yqszxx/yars/bv"
+	"github.com/yqszxx/yars/intf"
 	"log"
-	"yars/bv"
-	"yars/intf"
 )
 
 // LW loads a 32-bit value from memory, then sign-extends to 64-bits before storing in rd.

instruction/or.go

@@ -1,8 +1,8 @@
 package instruction
 
 import (
+	"github.com/yqszxx/yars/bv"
 	"log"
-	"yars/bv"
 )
 
 // OR performs bitwise OR logical operation.

instruction/ori.go

@@ -1,8 +1,8 @@
 package instruction
 
 import (
+	"github.com/yqszxx/yars/bv"
 	"log"
-	"yars/bv"
 )
 
 // ORI is a logical operation that performs bitwise OR on register rs1 and the sign-extended

instruction/sb.go

@@ -1,9 +1,9 @@
 package instruction
 
 import (
+	"github.com/yqszxx/yars/bv"
+	"github.com/yqszxx/yars/intf"
 	"log"
-	"yars/bv"
-	"yars/intf"
 )
 
 // The SB instruction stores 8-bit value from the low bits of register rs2 to memory.

instruction/sh.go

@@ -1,9 +1,9 @@
 package instruction
 
 import (
+	"github.com/yqszxx/yars/bv"
+	"github.com/yqszxx/yars/intf"
 	"log"
-	"yars/bv"
-	"yars/intf"
 )
 
 // The SH instruction stores 16-bit value from the low bits of register rs2 to memory.

instruction/sll.go

@@ -1,8 +1,8 @@
 package instruction
 
 import (
+	"github.com/yqszxx/yars/bv"
 	"log"
-	"yars/bv"
 )
 
 // SLL performs logical left shift on the value in register rs1 by the shift amount held in register

instruction/slli.go

@@ -1,8 +1,8 @@
 package instruction
 
 import (
+	"github.com/yqszxx/yars/bv"
 	"log"
-	"yars/bv"
 )
 
 // SLLI is a logical left shift (zeros are shifted into the lower bits). The operand to be shifted

instruction/slt.go

@@ -1,8 +1,8 @@
 package instruction
 
 import (
+	"github.com/yqszxx/yars/bv"
 	"log"
-	"yars/bv"
 )
 
 // SLT (set less than) performs signed compare, writing 1 to rd if rs1 < rs2, 0 otherwise.

instruction/slti.go

@@ -1,8 +1,8 @@
 package instruction
 
 import (
+	"github.com/yqszxx/yars/bv"
 	"log"
-	"yars/bv"
 )
 
 // SLTI (set less than immediate) places the value 1 in register rd if register rs1 is less than the

instruction/sltiu.go

@@ -1,8 +1,8 @@
 package instruction
 
 import (
+	"github.com/yqszxx/yars/bv"
 	"log"
-	"yars/bv"
 )
 
 // SLTIU (set less than immediate unsigned) places the value 1 in register rd if register rs1 is less

instruction/sltu.go

@@ -1,8 +1,8 @@
 package instruction
 
 import (
+	"github.com/yqszxx/yars/bv"
 	"log"
-	"yars/bv"
 )
 
 // SLTU (set less than) performs unsigned compare, writing 1 to rd if rs1 < rs2, 0 otherwise.

instruction/sra.go

@@ -1,8 +1,8 @@
 package instruction
 
 import (
+	"github.com/yqszxx/yars/bv"
 	"log"
-	"yars/bv"
 )
 
 // SRA performs arithmetic right shift on the value in register rs1 by the shift amount held in

instruction/srai.go

@@ -1,8 +1,8 @@
 package instruction
 
 import (
+	"github.com/yqszxx/yars/bv"
 	"log"
-	"yars/bv"
 )
 
 // SRAI is an arithmetic right shift (the original sign bit is copied into the vacated upper bits).

instruction/srl.go

@@ -1,8 +1,8 @@
 package instruction
 
 import (
+	"github.com/yqszxx/yars/bv"
 	"log"
-	"yars/bv"
 )
 
 // SRL performs logical right shift on the value in register rs1 by the shift amount held in register

instruction/srli.go

@@ -1,8 +1,8 @@
 package instruction
 
 import (
+	"github.com/yqszxx/yars/bv"
 	"log"
-	"yars/bv"
 )
 
 // SRLI is a logical right shift (zeros are shifted into the upper bits). The operand to be shifted

instruction/sub.go

@@ -1,8 +1,8 @@
 package instruction
 
 import (
+	"github.com/yqszxx/yars/bv"
 	"log"
-	"yars/bv"
 )
 
 // SUB performs subtraction. Overflows are ignored and the low 64 bits of results are written to

instruction/sw.go

@@ -1,9 +1,9 @@
 package instruction
 
 import (
+	"github.com/yqszxx/yars/bv"
+	"github.com/yqszxx/yars/intf"
 	"log"
-	"yars/bv"
-	"yars/intf"
 )
 
 // The SW instruction stores 32-bit value from the low bits of register rs2 to memory.

instruction/xor.go

@@ -1,8 +1,8 @@
 package instruction
 
 import (
+	"github.com/yqszxx/yars/bv"
 	"log"
-	"yars/bv"
 )
 
 // XOR performs bitwise XOR logical operation.

instruction/xori.go

@@ -1,8 +1,8 @@
 package instruction
 
 import (
+	"github.com/yqszxx/yars/bv"
 	"log"
-	"yars/bv"
 )
 
 // XORI is a logical operation that performs bitwise XOR on register rs1 and the sign-extended