Reduce patch noise

benches/predict.rs

@@ -127,7 +127,7 @@ pub fn intra_bench<T: Pixel>(
 ) {
   let mut rng = ChaChaRng::from_seed([0; 32]);
   let edge_buf = Aligned::from_fn(|_| T::cast_from(rng.gen::<u8>()));
-  let intra_edge = IntraEdge::mock(&edge_buf);
+  let edge_buf = IntraEdge::mock(&edge_buf);
   let (mut block, ac) = generate_block::<T>(&mut rng);
   let cpu = CpuFeatureLevel::default();
   let bitdepth = match T::type_enum() {
@@ -149,7 +149,7 @@ pub fn intra_bench<T: Pixel>(
       &ac,
       angle,
       None,
-      &intra_edge,
+      &edge_buf,
       cpu,
     );
   })

src/api/lookahead.rs

@@ -45,8 +45,6 @@ pub(crate) fn estimate_intra_costs<T: Pixel>(
   let w_in_imp_b = plane.cfg.width / IMPORTANCE_BLOCK_SIZE;
   let mut intra_costs = Vec::with_capacity(h_in_imp_b * w_in_imp_b);
 
-  let mut edge_buf = unsafe { Aligned::uninitialized() };
-
   for y in 0..h_in_imp_b {
     for x in 0..w_in_imp_b {
       let plane_org = plane.region(Area::Rect {
@@ -57,7 +55,8 @@ pub(crate) fn estimate_intra_costs<T: Pixel>(
       });
 
       // TODO: other intra prediction modes.
-      let intra_edge = get_intra_edges(
+      let mut edge_buf = unsafe { Aligned::uninitialized() };
+      let edge_buf = get_intra_edges(
         &mut edge_buf,
         &plane.as_region(),
         TileBlockOffset(BlockOffset { x, y }),
@@ -96,7 +95,7 @@ pub(crate) fn estimate_intra_costs<T: Pixel>(
         &[], // Not used by DC_PRED
         IntraParam::None,
         None, // Not used by DC_PRED
-        &intra_edge,
+        &edge_buf,
         cpu_feature_level,
       );
 

src/asm/aarch64/predict.rs

@@ -486,12 +486,12 @@ pub fn dispatch_predict_intra<T: Pixel>(
   mode: PredictionMode, variant: PredictionVariant,
   dst: &mut PlaneRegionMut<'_, T>, tx_size: TxSize, bit_depth: usize,
   ac: &[i16], angle: isize, ief_params: Option<IntraEdgeFilterParameters>,
-  intra_edge: &IntraEdge<T>, cpu: CpuFeatureLevel,
+  edge_buf: &IntraEdge<T>, cpu: CpuFeatureLevel,
 ) {
   let call_rust = |dst: &mut PlaneRegionMut<'_, T>| {
     rust::dispatch_predict_intra(
-      mode, variant, dst, tx_size, bit_depth, ac, angle, ief_params,
-      intra_edge, cpu,
+      mode, variant, dst, tx_size, bit_depth, ac, angle, ief_params, edge_buf,
+      cpu,
     );
   };
 
@@ -503,8 +503,8 @@ pub fn dispatch_predict_intra<T: Pixel>(
     let dst_ptr = dst.data_ptr_mut() as *mut _;
     let dst_u16 = dst.data_ptr_mut() as *mut u16;
     let stride = T::to_asm_stride(dst.plane_cfg.stride) as libc::ptrdiff_t;
-    let edge_ptr = intra_edge.top_left_ptr() as *const _;
-    let edge_u16 = intra_edge.top_left_ptr() as *const u16;
+    let edge_ptr = edge_buf.top_left_ptr() as *const _;
+    let edge_u16 = edge_buf.top_left_ptr() as *const u16;
     let w = tx_size.width() as libc::c_int;
     let h = tx_size.height() as libc::c_int;
     let angle = angle as libc::c_int;
@@ -597,7 +597,7 @@ pub fn dispatch_predict_intra<T: Pixel>(
             return ipred_z2(
               dst.data_ptr_mut(),
               stride,
-              intra_edge.top_left_ptr(),
+              edge_buf.top_left_ptr(),
               angle as isize,
               w,
               h,
@@ -611,7 +611,7 @@ pub fn dispatch_predict_intra<T: Pixel>(
           (if angle < 90 { ipred_z1 } else { ipred_z3 })(
             dst.data_ptr_mut(),
             stride,
-            intra_edge.top_left_ptr(),
+            edge_buf.top_left_ptr(),
             angle as isize,
             w,
             h,

src/asm/shared/predict.rs

@@ -44,7 +44,7 @@ mod test {
     let edge_buf = Aligned::from_fn(|i| {
       T::cast_from(((i ^ 1) + 32).saturating_sub(2 * MAX_TX_SIZE))
     });
-    let intra_edge = IntraEdge::mock(&edge_buf);
+    let edge_buf = IntraEdge::mock(&edge_buf);
 
     let ief_params_all = [
       None,
@@ -129,7 +129,7 @@ mod test {
               &ac.data,
               *angle,
               *ief_params,
-              &intra_edge,
+              &edge_buf,
               cpu,
             );
             let mut data = [T::zero(); 4 * 4];
@@ -149,7 +149,7 @@ mod test {
             &ac.data,
             *angle,
             *ief_params,
-            &intra_edge,
+            &edge_buf,
             cpu,
           );
           assert_eq!(

src/asm/x86/predict.rs

@@ -240,12 +240,12 @@ pub fn dispatch_predict_intra<T: Pixel>(
   mode: PredictionMode, variant: PredictionVariant,
   dst: &mut PlaneRegionMut<'_, T>, tx_size: TxSize, bit_depth: usize,
   ac: &[i16], angle: isize, ief_params: Option<IntraEdgeFilterParameters>,
-  intra_edge: &IntraEdge<T>, cpu: CpuFeatureLevel,
+  edge_buf: &IntraEdge<T>, cpu: CpuFeatureLevel,
 ) {
   let call_rust = |dst: &mut PlaneRegionMut<'_, T>| {
     rust::dispatch_predict_intra(
-      mode, variant, dst, tx_size, bit_depth, ac, angle, ief_params,
-      intra_edge, cpu,
+      mode, variant, dst, tx_size, bit_depth, ac, angle, ief_params, edge_buf,
+      cpu,
     );
   };
 
@@ -259,7 +259,7 @@ pub fn dispatch_predict_intra<T: Pixel>(
     match T::type_enum() {
       PixelType::U8 => {
         let dst_ptr = dst.data_ptr_mut() as *mut _;
-        let edge_ptr = intra_edge.top_left_ptr() as *const _;
+        let edge_ptr = edge_buf.top_left_ptr() as *const _;
         if cpu >= CpuFeatureLevel::AVX512ICL {
           match mode {
             PredictionMode::DC_PRED => {
@@ -552,7 +552,7 @@ pub fn dispatch_predict_intra<T: Pixel>(
       }
       PixelType::U16 => {
         let dst_ptr = dst.data_ptr_mut() as *mut _;
-        let edge_ptr = intra_edge.top_left_ptr() as *const _;
+        let edge_ptr = edge_buf.top_left_ptr() as *const _;
         let bd_max = (1 << bit_depth) - 1;
         if cpu >= CpuFeatureLevel::AVX512ICL {
           match mode {

src/encoder.rs

@@ -1474,9 +1474,9 @@ pub fn encode_tx_block<T: Pixel, W: Writer>(
   let rec = &mut ts.rec.planes[p];
 
   if mode.is_intra() {
-    let mut edge_buf = unsafe { Aligned::uninitialized() };
     let bit_depth = fi.sequence.bit_depth;
-    let intra_edge = get_intra_edges(
+    let mut edge_buf = unsafe { Aligned::uninitialized() };
+    let edge_buf = get_intra_edges(
       &mut edge_buf,
       &rec.as_const(),
       tile_partition_bo,
@@ -1499,7 +1499,7 @@ pub fn encode_tx_block<T: Pixel, W: Writer>(
       ac,
       pred_intra_param,
       ief_params,
-      &intra_edge,
+      &edge_buf,
       fi.cpu_feature_level,
     );
   }

src/predict.rs

@@ -204,7 +204,7 @@ impl PredictionMode {
   pub fn predict_intra<T: Pixel>(
     self, tile_rect: TileRect, dst: &mut PlaneRegionMut<'_, T>,
     tx_size: TxSize, bit_depth: usize, ac: &[i16], intra_param: IntraParam,
-    ief_params: Option<IntraEdgeFilterParameters>, intra_edge: &IntraEdge<T>,
+    ief_params: Option<IntraEdgeFilterParameters>, edge_buf: &IntraEdge<T>,
     cpu: CpuFeatureLevel,
   ) {
     assert!(self.is_intra());
@@ -242,8 +242,8 @@ impl PredictionMode {
     };
 
     dispatch_predict_intra::<T>(
-      mode, variant, dst, tx_size, bit_depth, ac, angle, ief_params,
-      intra_edge, cpu,
+      mode, variant, dst, tx_size, bit_depth, ac, angle, ief_params, edge_buf,
+      cpu,
     );
   }
 
@@ -711,13 +711,13 @@ pub(crate) mod rust {
     mode: PredictionMode, variant: PredictionVariant,
     dst: &mut PlaneRegionMut<'_, T>, tx_size: TxSize, bit_depth: usize,
     ac: &[i16], angle: isize, ief_params: Option<IntraEdgeFilterParameters>,
-    intra_edge: &IntraEdge<T>, _cpu: CpuFeatureLevel,
+    edge_buf: &IntraEdge<T>, _cpu: CpuFeatureLevel,
   ) {
     let width = tx_size.width();
     let height = tx_size.height();
 
     // left pixels are ordered from bottom to top and right-aligned
-    let (left, top_left, above) = intra_edge.as_slices();
+    let (left, top_left, above) = edge_buf.as_slices();
 
     let above_slice = above;
     let left_slice = &left[left.len().saturating_sub(height)..];

src/rdo.rs

@@ -1434,7 +1434,7 @@ fn intra_frame_rdo_mode_decision<T: Pixel>(
       // FIXME: If tx partition is used, this whole sads block should be fixed
       let tx_size = bsize.tx_size();
       let mut edge_buf = unsafe { Aligned::uninitialized() };
-      let intra_edge = {
+      let edge_buf = {
         let rec = &ts.rec.planes[0].as_const();
         let po = tile_bo.plane_offset(rec.plane_cfg);
         // FIXME: If tx partition is used, get_intra_edges() should be called for each tx block
@@ -1481,7 +1481,7 @@ fn intra_frame_rdo_mode_decision<T: Pixel>(
           &[0i16; 2],
           IntraParam::None,
           if luma_mode.is_directional() { ief_params } else { None },
-          &intra_edge,
+          &edge_buf,
           fi.cpu_feature_level,
         );
 
@@ -1614,7 +1614,6 @@ pub fn rdo_cfl_alpha<T: Pixel>(
   // SAFETY: We write to the array below before reading from it.
   let mut ac: Aligned<[MaybeUninit<i16>; 32 * 32]> =
     unsafe { Aligned::uninitialized() };
-  let mut edge_buf = unsafe { Aligned::uninitialized() };
   let ac = luma_ac(&mut ac.data, ts, tile_bo, bsize, luma_tx_size, fi);
   let best_alpha: ArrayVec<i16, 2> = (1..3)
     .map(|p| {
@@ -1623,7 +1622,8 @@ pub fn rdo_cfl_alpha<T: Pixel>(
       let rec = &mut ts.rec.planes[p];
       let input = &ts.input_tile.planes[p];
       let po = tile_bo.plane_offset(rec.plane_cfg);
-      let intra_edge = get_intra_edges(
+      let mut edge_buf = unsafe { Aligned::uninitialized() };
+      let edge_buf = get_intra_edges(
         &mut edge_buf,
         &rec.as_const(),
         tile_bo,
@@ -1648,7 +1648,7 @@ pub fn rdo_cfl_alpha<T: Pixel>(
           ac,
           IntraParam::Alpha(alpha),
           None,
-          &intra_edge,
+          &edge_buf,
           fi.cpu_feature_level,
         );
         sse_wxh(