DigitalTrafficController

curriculum design of digital logic. I completed it in verilog with Xilinx ISE 14.2.

Name		Name	Last commit message	Last commit date
Latest commit History 4 Commits
DECODE7.v		DECODE7.v
FDIVISION.v		FDIVISION.v
LICENSE		LICENSE
MAIN.ucf		MAIN.ucf
MAIN.v		MAIN.v
README.md		README.md
TRAFFIC.v		TRAFFIC.v

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