ECS

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Project for Electronic and Communication Systems course

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Simple programmable pulse generator circuit write in VHDL language. Xilinx Vivado tool used for synthesis.

Developed by Valerio Tanferna

Name		Name	Last commit message	Last commit date
Latest commit History 3 Commits
GIP.vhd		GIP.vhd
README.md		README.md
Relazione.pdf		Relazione.pdf
_DS_Store		_DS_Store
adder.vhd		adder.vhd
counter.vhd		counter.vhd
creg.vhd		creg.vhd
gen_pulse.vhd		gen_pulse.vhd
generatore di impulsi programmabile.pdf		generatore di impulsi programmabile.pdf
reg.vhd		reg.vhd
sreg.vhd		sreg.vhd
tbGIP.vhd		tbGIP.vhd
tbadder.vhd		tbadder.vhd
tbcounter.vhd		tbcounter.vhd
tbcreg.vhd		tbcreg.vhd
tbgen_pulse.vhd		tbgen_pulse.vhd
tbreg.vhd		tbreg.vhd
tbsreg.vhd		tbsreg.vhd