Bump qs from 6.10.1 to 6.13.1 in /mlir/utils/vscode #8
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…7074) We do not have support for the threadsafe statics on the GPU side. However, we do sometimes end up with empty local static initializers, and those happen to trigger calls to `__cxa_guard*`, which breaks compilation. Partially addresses llvm#117023
- define intrinsic as builtin in Builtins.td
- link intrinsic in hlsl_intrinsics.h
- add semantic analysis to SemaHLSL.cpp
- lower to `llvm` or a `dx` intrinsic when applicable in CGBuiltin.cpp
- define DXIL intrinsic in IntrinsicsDirectX.td
- add DXIL op and mapping in DXIL.td
- enable scalarization of intrinsic
- add basic sema checking to asdouble-errors.hlsl
Resolves llvm#99081
…lvm#117266) Add a pythonic `stop_reason_data` property to `SBThread`. The property produces a list of ints.
Move-assignment is quite convenient in various situation, and work-around having it available is very convoluted.
The only way to test `getInversePermutation` is through unit tests. The concept of "inverse permutations" is tricky to document and these tests are a good source documentation of the expected/intended behavoiur. Hence these additional unit tests. This is a follow-on of llvm#114775 in which I added tests for `isProjectedPermutation`.
The Intel X86 Architecture Manual says the following: > A REX prefix is ignored, as are its individual bits, when it is not needed > for an instruction or when it does not immediately precede the opcode byte or > the escape opcode byte (0FH) of an instruction for which it is needed. This > has the implication that only one REX prefix, properly located, can affect an > instruction. We currently do not handle these cases in the disassembler, leading to incorrect disassembly. This patch rectifies the situation by treating REX prefixes as standard prefixes rather than only expecting them before the Opcode. The motivating test case added as a test was fuzzer generated.
…lvm#117199) The aliases are -mcpu=help and -mtune=help. There is still an issue with the output which prints an example line that references clang. That is not fixed here because it is printed in llvm/MC/SubtargetInfo.cpp. Some more thought is needed to determine how best to handle this. Fixes llvm#117010
…m#116248)" (llvm#117365) Maybe not needed but to avoid conflicts with llvm#117307 Without revert of this one, but reverting llvm#117307, the regenerated init-undef.mir became empty. This reverts commit be15fd5.
Following llvm#116547, this changes the result of `ARMISD::CMPFP*` and the operand of `ARMISD::FMSTAT` from a special `Glue` type to a normal type. This change allows comparisons to be CSEd and scheduled around as can be seen in the test changes. Note that `ARMISD::FMSTAT` is still glued to its consumer nodes; this is going to be changed in a separate patch. This patch also sets `CopyCost` of `cl_FPSCR_NZCV` register class to a negative value. The reason is the same as for CCR register class: it makes DAG scheduler and InstrEmitter try to avoid copies of `FPCSR_NZCV` register to / from virtual registers. Previously, this was not necessary, since no attempt was made to create copies in the first place. `TRI::getCrossCopyRegClass` is modified in a way that prevents DAG scheduler from copying FPSCR into a virtual register. The register allocator might need to spill the virtual register, but that only seem to work in Thumb mode.
…zing. (llvm#116191)" (llvm#117367) To pass tests with llvm#117307 revert. This reverts commit 3093b29.
…lvm#114827)" (llvm#117307) Details in llvm#114827 This reverts commit c1c68ba.
…m#114447) Sometimes we want to use a `PgoAnalysisMap` feature that doesn't require the BB entries info, e.g. only the `FuncEntryCount`, but the BB entries is emitted by default, so I'm adding an option to skip the info for this case to save the binary size(can save ~90% size of the section). For implementation, it extends a new field(`OmitBBEntries`) in `BBAddrMap::Features` for this and it's controlled by a switch `--basic-block-address-map-skip-bb-entries`. Note that this naturally supports backwards compatibility as the field is zero for the old version, matches the decoding in the new version llvm.
This patch removes MemProf format Version 1 now that Version 2 and 3 are working well.
I got asked about this offline and realized we didn't really have tests specific to the VLS frame lowering.
Verify the format is valid and the type is one of the expected i32 vectors. Verify the used vector types at least cover the requirements of the corresponding format operand.
…analysis (llvm#117324) Doug implemented quite literally all of it and has been continuously improving the implementation by handling more language constructs we had initially missed. I spent a lot of time reviewing the implementation of the attributes as well as the analysis pass, so in other words, the two of us are probably best equipped to answer any questions that might arise wrt this part of Clang.
Patch allows to vector scalar instruction + poison values as if poisons are instructions with the same opcode. It allows better vectorization of the repeated values, reduces number of insertelement instructions and serves as a base ground for copyable elements vectorization AVX512, -O3 + LTO JM/ldecod - better vector code Applications/oggenc - better vectorization CINT2017speed/625.x264_s CINT2017rate/525.x264_r - better vector code CFP2017rate/526.blender_r - better vector code CFP2006/447.dealII - small variations Benchmarks/Bullet - extra vector code CFP2017rate/510.parest_r - better vectorization CINT2017rate/502.gcc_r CINT2017speed/602.gcc_s - extra vector code Benchmarks/tramp3d-v4 - small variations CFP2006/453.povray - extra vector code JM/lencod - better vector code CFP2017rate/511.povray_r - extra vector code MemFunctions/MemFunctions - extra vector code LoopVectorization/LoopVectorizationBenchmarks - extra vector code XRay/FDRMode - extra vector code XRay/ReturnReference - extra vector code LCALS/SubsetCLambdaLoops - extra vector code LCALS/SubsetCRawLoops - extra vector code LCALS/SubsetARawLoops - extra vector code LCALS/SubsetALambdaLoops - extra vector code DOE-ProxyApps-C++/miniFE - extra vector code LoopVectorization/LoopInterleavingBenchmarks - extra vector code LCALS/SubsetBLambdaLoops - extra vector code MicroBenchmarks/harris - extra vector code ImageProcessing/Dither - extra vector code MicroBenchmarks/SLPVectorization - extra vector code ImageProcessing/Blur - extra vector code ImageProcessing/Dilate - extra vector code Builtins/Int128 - extra vector code ImageProcessing/Interpolation - extra vector code ImageProcessing/BilateralFiltering - extra vector code ImageProcessing/AnisotropicDiffusion - extra vector code MicroBenchmarks/LoopInterchange - extra code vectorized LCALS/SubsetBRawLoops - extra code vectorized CINT2006/464.h264ref - extra vectorization with wider vectors CFP2017rate/508.namd_r - small variations, extra phis vectorized CFP2006/444.namd - 2 2 x phi replaced by 4 x phi DOE-ProxyApps-C/SimpleMOC - extra code vectorized CINT2017rate/541.leela_r CINT2017speed/641.leela_s - the function better vectorized and inlined Benchmarks/Misc/oourafft - 2 4 x bit reductions replaced by 2 x vector code FreeBench/fourinarow - better vectorization Reviewers: RKSimon Reviewed By: RKSimon Pull Request: llvm#115946
Patch uses getExtendedReduction for reductions of ext-based nodes + adds cost estimation for ctpop-kind reductions into basic implementation and RISCV-V specific vcpop cost estimation. Reviewers: RKSimon, preames Reviewed By: preames Pull Request: llvm#117350
Extend existing store widening pass to widen load instructions. This patch also borrows the alias check algorithm from AMDGPU's load store widening pass. Widened load instruction is inserted before the first candidate load instruction. Widened store instruction is inserted after the last candidate store instruction. This method helps avoid moving uses/defs when replacing load/store instructions with their widened equivalents. The pass has also been extended to * Generate 64-bit widened stores * Handle 32-bit post increment load/store * Handle stores of non-immediate values * Handle stores where the offset is a GlobalValue
A recent commit (23d7a6c) introduced a dependency on libLLVMMC.so. This is to handle the `-print-supported-cpus` option which uses `llvm/MC/SubtargetInfo`. It requires libLLVMMC to be linked into the flang-driver which the previous commit did not do. This fixes that issue.
Summary: Previous patches have made the `rpc.h` header independent of the `libc` internals. This allows us to include it directly rather than providing an indirect C API. This patch only does the work to move the header. A future patch will pull out the `rpc_server` interface and simply replace it with a single function that handles the opcodes.
Turns out there were also errors in the recvfrom unpoisoning logic. This patch fixes those.
Unfortunately there's no upstream frontend for Metal but since the id's are now assigned by the DWARF standard I think it makes sense to have the enums upstream to enable tools like llvm-dwarfdump. This patch therefore uses an AArch64 test with artificially modified debug info to verify that the Metal language id can be used. https://dwarfstd.org/issues/241111.1.html
… ISel (llvm#117375) This removes operands/results either in SDNode description or in ISel code so that they match each other.
This comes up when intercepting clang-built `__sanitizer_cov` functions.
The R_ARM_SBREL32 relocation is used in debug info for ARM RWPI (read-write position independent) code. Compiler-generated DWARF info will use an expression to add the relocated value to the actual value of the static base (held in r9) at run-time, so it should be relocated as if the static base is at address 0.
In llvm#108907, the index classes started filtering the DIEs according to the full type query (instead of just the base name). This means that the checks in SymbolFileDWARF are now redundant. I've also moved the non-redundant checks so that now all checking is done in the DWARFIndex class and the caller can expect to get the final filtered list of types.
We currently list Evan Cheng as the fallback maintainer for the LLVM backend. However, their last contribution dates back to 2014. I'd like to nominate arsenm instead, who is our most active backend reviewer.
This PR extracts NFC changes out of llvm#116035 to reap as many of the same benefits without any of the semantic changes. More concretely, moving `LLVMStructType` to ODS has the benefits of being able to generate much of the required boilerplate, such as interface definitions, documentation and more, automatically. Furthermore, `LLVMStructType` is then treated less special and its definition can be found at the same place where all other complex type definitions are found in the LLVM dialect. Future changes could leverage more automatically generated code from TableGen such as `assemblyFormat`. As these are not as trivial, they have been left for future PRs. --------- Co-authored-by: Tobias Gysi <[email protected]>
…7110)" (llvm#117128) Remain InheritableAttr to avoid the warning `TypePrinter.cpp:1953:10: warning: enumeration value ‘TargetVersion’ not handled in switch` origin messenge [TargetVersion] Only enable on RISC-V and AArch64 (llvm#115991) Address llvm#115000. This patch constrains the target_version feature to work only on RISC-V and AArch64 to prevent crashes in Clang. Co-authored-by: Aaron Ballman <[email protected]>
We currently support simple reassociation for foldAndOrOfICmps(). Support the same for foldLogicOfFCmps() by going through the common foldBooleanAndOr() helper. This will also resolve the regression on llvm#112704, which is also due to missing reassoc support. I had to adjust one fold to add support for FMF flag preservation, otherwise there would be test regressions. There is a separate fold (reassociateFCmps) handling reassociation for *just* that specific case and it preserves FMF. Unfortunately it's not rendered entirely redundant by this patch, because it handles one more level of reassociation as well.
…lvm#116031) For IR like this: %icmp = icmp ult <4 x i32> %a, splat (i32 5) %res = extractelement <4 x i1> %icmp, i32 1 where there is only one use of %icmp we can take a similar approach to what we already do for binary ops such add, sub, etc. and convert this into %ext = extractelement <4 x i32> %a, i32 1 %res = icmp ult i32 %ext, 5 For AArch64 targets at least the scalar boolean result will almost certainly need to be in a GPR anyway, since it will probably be used by branches for control flow. I've tried to reuse existing code in scalarizeExtractedBinop to also work for setcc. NOTE: The optimisations don't apply for tests such as extract_icmp_v4i32_splat_rhs in the file CodeGen/AArch64/extract-vector-cmp.ll because scalarizeExtractedBinOp only works if one of the input operands is a constant.
To guard against regression from llvm#112704.
As with other operations we scalarize any vectors with larger types to let the scalare legalization kick in.
To guard against regression from llvm#117182.
This is split off from llvm#115274. There doesn't seem to be an easy way to share this with getShuffleCost since that requires passing in a real insert_element operand to get it to recognise it's a scalar splat. For i1 vectors we can't currently lower them so it returns an invalid cost. --------- Co-authored-by: Shih-Po Hung <[email protected]>
Fold `llvm.amdgcn.wavefrontsize` early, during InstCombine, so that it's concrete value is used throughout subsequent optimisation passes.
This PR adds support seq_cst (sequential consistency) clause for the flush directive in OpenMP. The seq_cst clause enforces a stricter memory ordering, ensuring that all threads observe the memory effects of the flush in the same order, improving consistency in memory operations across threads. --------- Co-authored-by: Shashwathi N <[email protected]> Co-authored-by: CHANDRA GHALE <[email protected]>
Equality/inequality of the low bit can be represented by `(trunc (xor x, y) to i1)`, possibly with an extra not. We have to handle this in the eq-of-parts fold now that we no longer canonicalize this to a masked icmp. Proofs: https://alive2.llvm.org/ce/z/qidkzq Fixes llvm#110919.
…lvm#117312) The attached test case from llvm#117294 used to cause an assertion because we called classifPrim() on an array type. The new result doesn't crash but isn't exactly perfect either. Since the problem arises when evaluating an ImplicitValueInitExpr, we have no proper source location to point to. Point to the caller instead.
…117352) This generated comments like: // 'BoolReg' class case MCK_BoolReg: { which seem redundant because the name is always repeated on the next line as part of the MCK_ enumerator.
This PR adds the missing `const override` to the `rewrite` and `matchAndRewrite` declaration in the Pattern Rewriter documentation as described here: https://github.com/llvm/llvm-project/blob/5cfa8baef33636827e5aa8dd76888c724433b53e/mlir/include/mlir/IR/PatternMatch.h#L237-L265
…ns (llvm#115745) * Enables conversion of several select-like instructions within one group * Any number of auxiliary instructions depending on the same condition can be in between select-like instructions * After splitting the basic block, move select-like instructions into the relevant basic blocks and optimise them * Make it easier to add support shift-base select-like instructions and also any mixture of zext/sext/not instructions
llvm#92815) When a binary has multiple text segments, the Size is computed as the difference of the last address of these segments from the BaseAddress. The base addresses of all text segments must be the same. Introduces flag 'perf-script-events' for testing. It allows passing perf events without BOLT having to parse them using 'perf script'. The flag is used to pass a mock perf profile that has two memory mappings for a mock binary that has two text segments. The size of the mapping is updated as this change `parseMMapEvents` processes all text segments.
In offline mode, the script sets 'PASS' variable and does not use it. Surrounding code suggests using 'FAIL' variable instead.
Summary: This patch removes much of the `llvmlibc_rpc_server` interface. This pretty much deletes all of this code and just replaces it with including `rpc.h` directly. We still maintain the file to let `libc` handle the opcodes, since those depend on the `printf` impelmentation. This will need to be cleaned up more, but I don't want to put too much into a single patch.
Bumps [qs](https://github.com/ljharb/qs) from 6.10.1 to 6.13.1. - [Changelog](https://github.com/ljharb/qs/blob/main/CHANGELOG.md) - [Commits](ljharb/qs@v6.10.1...v6.13.1) --- updated-dependencies: - dependency-name: qs dependency-type: indirect ... Signed-off-by: dependabot[bot] <[email protected]>
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Bumps qs from 6.10.1 to 6.13.1.
Changelog
Sourced from qs's changelog.
... (truncated)
Commits
f1ee037v6.13.1afd20d0[Dev Deps] updateobject-inspectd185cee[actions] split out node 10-20, and 20+4cf5567[Dev Deps] updatees-value-fixtures,tape3c8a6f5[Refactor] use__proto__syntax instead ofObject.createfor null objects96f4d93[Fix]stringify: avoid a crash when afilterkey isnullaa1f0a8[Fix]utils.merge: functions should not be stringified into keys2a548a9[Tests]utils.merge: add some coverage3e750c1[Refactor] misc cleanupca55d0f[Fix]parse: avoid a crash with interpretNumericEntities: true, comma: true...Dependabot will resolve any conflicts with this PR as long as you don't alter it yourself. You can also trigger a rebase manually by commenting
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