Analog-Signal-Interfacing-and-Filtering-using-FPGA-in-VHDL

Reading the digitized values of an analog signal connected to ADC input on Spartan 3E board, doing some digital filtering on the samples and providing the output through DAC on board. Displaying both the input and output on an Oscilloscope. You can also use Pmod ADC with BASYS3 Board.

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Reference Documents:

• Design_Details
• Component_Schematics
• Filter_Simulation_Results
• Practical_Results

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Source Code and Desiged Blocks

• Main Source Code Filter_main

• Components Source Code:

  • Clock Divider clk_divider
  • ADC Controller XADC_Comp
  • DAC Controller DA2_Comp
  • FIR Filter Filter_comp

• Testbench:

  • Main Testbench filter_main_tb

• Filter Standalone Code:

  • FIR Filter RTL Code Filter_fir
  • Filter Testbench filter_tb_2

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Bitstream file:

Filter_main.bit

Bitstream is generated for Digilent Basys 3 FPGA board.

Basys 3 Constraint File constraints_basys3.xdc

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Block Diagram of the Complete Design

Complete Setup (Wiring Connections):