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Fix Rx issues #162

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Dec 5, 2023
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9 changes: 1 addition & 8 deletions LCLS-II/core/rtl/GthRxAlignCheck.vhd
Original file line number Diff line number Diff line change
Expand Up @@ -108,13 +108,6 @@ architecture rtl of GthRxAlignCheck is

signal txClkFreq : slv(31 downto 0);
signal rxClkFreq : slv(31 downto 0);

-- attribute dont_touch : string;
-- attribute dont_touch of r : signal is "TRUE";
-- attribute dont_touch of ack : signal is "TRUE";
-- attribute dont_touch of txClkFreq : signal is "TRUE";
-- attribute dont_touch of rxClkFreq : signal is "TRUE";

begin

U_txClkFreq : entity surf.SyncClockFreq
Expand Down Expand Up @@ -244,7 +237,7 @@ begin
end if;

-- Check for user reset
if (resetIn = '1') or (resetErr = '1') then
if (resetIn = '1') or (resetErr = '1' and resetDone = '1') then
-- Setup flags for reset state
v.rst := '1';
v.req.request := '0';
Expand Down
4 changes: 2 additions & 2 deletions LCLS-II/core/rtl/TimingDeserializer.vhd
Original file line number Diff line number Diff line change
Expand Up @@ -79,9 +79,9 @@ architecture TimingDeserializer of TimingDeserializer is
signal r : RegType := REG_INIT_C;
signal rin : RegType;
signal crc : slv(31 downto 0);

begin

fiducial <= r.fiducial;
streams <= r.streams;
advance <= r.advance;
Expand Down
2 changes: 1 addition & 1 deletion LCLS-II/core/rtl/TimingFrameRx.vhd
Original file line number Diff line number Diff line change
Expand Up @@ -83,7 +83,7 @@ architecture rtl of TimingFrameRx is
signal dframe : DataArray;
signal dstrobe : slv(15 downto 1);
signal dvalid : slv(15 downto 1);

begin

delayRst <= rxRst or messageDelayRst or doverflow0;
Expand Down
3 changes: 1 addition & 2 deletions LCLS-II/core/rtl/TimingRx.vhd
Original file line number Diff line number Diff line change
Expand Up @@ -139,7 +139,6 @@ architecture rtl of TimingRx is
signal timingTSEventCounter : slv(31 downto 0);
signal timingTSEvCntGray_i : slv(31 downto 0);
signal timingTSEvCntGray_o : Slv32Array(5 downto 0);

begin

NOGEN_RxLcls1 : if (CLKSEL_MODE_G = "LCLSII" or CLKSEL_MODE_G = "LCLSIIPIC") generate
Expand Down Expand Up @@ -194,7 +193,7 @@ begin
rxVersion => rxVersion(1),
staData => staData (1));
end generate;

axilComb : process (axilR, axilRst, axilReadMaster, axilRxLinkUp, axilStatusCounters12,
axilStatusCounters3, axilVersion, axilVsnErr, axilWriteMaster, rxStatusCount,
timingTSEvCntGray_o, txClkCntS) is
Expand Down
4 changes: 2 additions & 2 deletions LCLS-II/gthUltraScale+/coregen/TimingGth_extref.dcp
Git LFS file not shown
2,368 changes: 924 additions & 1,444 deletions LCLS-II/gthUltraScale+/coregen/TimingGth_extref.xci

Large diffs are not rendered by default.

4 changes: 2 additions & 2 deletions LCLS-II/gthUltraScale+/coregen/TimingGth_fixedlat.dcp
Git LFS file not shown
2,440 changes: 926 additions & 1,514 deletions LCLS-II/gthUltraScale+/coregen/TimingGth_fixedlat.xci

Large diffs are not rendered by default.

4 changes: 3 additions & 1 deletion LCLS-II/gthUltraScale+/rtl/TimingGthCoreWrapper.vhd
Original file line number Diff line number Diff line change
Expand Up @@ -81,6 +81,7 @@ entity TimingGthCoreWrapper is
txOutClk : out sl;

loopback : in slv(2 downto 0));

end entity TimingGthCoreWrapper;

architecture rtl of TimingGthCoreWrapper is
Expand Down Expand Up @@ -473,7 +474,8 @@ begin
O => rxoutclkb);
end generate;

LOCREF_G : if (DISABLE_TIME_GT_G = false) and (EXTREF_G = false)generate
LOCREF_G : if (DISABLE_TIME_GT_G = false) and (EXTREF_G = false) generate

U_TimingGthCore : TimingGth_fixedlat
port map (
gtwiz_userclk_tx_reset_in(0) => txbypassrst,
Expand Down
10 changes: 4 additions & 6 deletions LCLS-II/gthUltraScale+/ruckus.tcl
Original file line number Diff line number Diff line change
@@ -1,16 +1,14 @@
# Load RUCKUS environment and library
source -quiet $::env(RUCKUS_DIR)/vivado_proc.tcl

if { $::env(VIVADO_VERSION) >= 2021.2 } {

if { $::env(VIVADO_VERSION) >= 2022.2} {
loadSource -lib lcls_timing_core -dir "$::DIR_PATH/rtl"

loadSource -lib lcls_timing_core -path "$::DIR_PATH/coregen/TimingGth_extref.dcp"
# loadIpCore -path "$::DIR_PATH/coregen/TimingGth_extref.xci"
#loadIpCore -path "$::DIR_PATH/coregen/TimingGth_extref.xci"

loadSource -lib lcls_timing_core -path "$::DIR_PATH/coregen/TimingGth_fixedlat.dcp"
# loadIpCore -path "$::DIR_PATH/coregen/TimingGth_fixedlat.xci"

#loadIpCore -path "$::DIR_PATH/coregen/TimingGth_fixedlat.xci"
} else {
puts "\n\nWARNING: $::DIR_PATH requires Vivado 2021.2 (or later)\n\n"
puts "\n\nWARNING: $::DIR_PATH requires Vivado 2022.2 (or later)\n\n"
}
10 changes: 10 additions & 0 deletions python/LclsTimingCore/GthRxAlignCheck.py
Original file line number Diff line number Diff line change
Expand Up @@ -61,6 +61,16 @@ def __init__( self,
mode = "RW",
))


self.add(pr.RemoteVariable(
name = "Mask",
description = "Mask",
offset = 0x100,
bitSize = 7,
bitOffset = 8,
mode = "RW",
))

self.add(pr.RemoteVariable(
name = "ResetLen",
description = "Reset length",
Expand Down