Add xor complementary trigger logic

slaclab · Feb 26, 2024 · f1b7f58 · f1b7f58
1 parent 54d12cb
commit f1b7f58
Show file tree

Hide file tree

Showing 3 changed files with 11 additions and 8 deletions.
diff --git a/LCLS-II/evr/rtl/EvrV2Pkg.vhd b/LCLS-II/evr/rtl/EvrV2Pkg.vhd
@@ -68,13 +68,13 @@ package EvrV2Pkg is
   type EvrV2ChannelConfigArray is array (natural range<>) of EvrV2ChannelConfig;
 
   constant EVRV2_TRIG_WIDTH_C : integer := 28;
-  constant EVRV2_TRIGGER_CONFIG_BITS_C : integer := 31+2*EVRV2_TRIG_WIDTH_C;
+  constant EVRV2_TRIGGER_CONFIG_BITS_C : integer := 32+2*EVRV2_TRIG_WIDTH_C;
 
   type EvrV2TriggerConfigType is record
     enabled  : sl;
     polarity : sl;
     complEn  : sl;
-    complAnd : sl;
+    complOp  : slv( 1 downto 0);
     delay    : slv(EVRV2_TRIG_WIDTH_C-1 downto 0);
     width    : slv(EVRV2_TRIG_WIDTH_C-1 downto 0);
     channel  : slv( 3 downto 0);
@@ -87,7 +87,7 @@ package EvrV2Pkg is
     enabled   => '0',
     polarity  => '1',
     complEn   => '0',
-    complAnd  => '0',
+    complOp   => "00",
     delay     => (others=>'0'),
     width     => toSlv(1, EVRV2_TRIG_WIDTH_C), -- Default to 1 cycle width, 0 will essentially disable the channel (zero cycle wide)
     channel   => (others=>'0'),

diff --git a/LCLS-II/evr/rtl/EvrV2TrigReg.vhd b/LCLS-II/evr/rtl/EvrV2TrigReg.vhd
@@ -83,7 +83,7 @@ begin
          axiSlaveRegister(axilEp, toSlv(i*GRP_C + 0, STRIDE_C), 0, v.triggerConfig(i).channel);
          axiSlaveRegister(axilEp, toSlv(i*GRP_C + 0, STRIDE_C), 16, v.triggerConfig(i).polarity);
          axiSlaveRegister(axilEp, toSlv(i*GRP_C + 0, STRIDE_C), 28, v.triggerConfig(i).complEn);
-         axiSlaveRegister(axilEp, toSlv(i*GRP_C + 0, STRIDE_C), 29, v.triggerConfig(i).complAnd);
+         axiSlaveRegister(axilEp, toSlv(i*GRP_C + 0, STRIDE_C), 29, v.triggerConfig(i).complOp);
          axiSlaveRegister(axilEp, toSlv(i*GRP_C + 0, STRIDE_C), 31, v.triggerConfig(i).enabled);
          axiSlaveRegister(axilEp, toSlv(i*GRP_C + 4, STRIDE_C), 0, v.triggerConfig(i).delay);
          axiSlaveRegister(axilEp, toSlv(i*GRP_C + 8, STRIDE_C), 0, v.triggerConfig(i).width);

diff --git a/LCLS-II/evr/rtl/EvrV2TriggerCompl.vhd b/LCLS-II/evr/rtl/EvrV2TriggerCompl.vhd
@@ -64,11 +64,14 @@ begin
    begin
       for i in 0 to 1 loop
          if config(i).complEn = '0' then
-            v.trig(i) := trigIn(i);
-         elsif config(i).complAnd = '1' then
-            v.trig(i) := trigIn(0) and trigIn(1);
+           v.trig(i) := trigIn(i);
          else
-            v.trig(i) := trigIn(0) or trigIn(1);
+           case config(i).complOp is
+             when "00" => v.trig(i) <=     trigIn(0) or  trigIn(1);
+             when "01" => v.trig(i) <=     trigIn(0) and trigIn(1);
+             when "10" => v.trig(i) <=     trigIn(0) xor trigIn(1);
+             when "11" => v.trig(i) <= '1';  -- reserved
+           end case;
          end if;
       end loop;