migrating from lcls_timing_core.GthRxAlignCheck to surf.GtRxAlignCheck

slaclab · Jan 14, 2025 · 9122f5b · 9122f5b
1 parent 6ed8c16
commit 9122f5b
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Showing 3 changed files with 17 additions and 9 deletions.
diff --git a/LCLS-II/gthUltraScale+/rtl/TimingGthCoreWrapper.vhd b/LCLS-II/gthUltraScale+/rtl/TimingGthCoreWrapper.vhd
@@ -31,6 +31,7 @@ use unisim.vcomponents.all;
 entity TimingGthCoreWrapper is
    generic (
       TPD_G             : time             := 1 ns;
+      SIMULATION_G      : boolean          := false;
       DISABLE_TIME_GT_G : boolean          := false;
       EXTREF_G          : boolean          := false;
       AXIL_BASE_ADDR_G  : slv(31 downto 0);
@@ -302,15 +303,18 @@ begin
          mAxiReadMasters     => axilReadMasters,
          mAxiReadSlaves      => axilReadSlaves);
 
-   U_AlignCheck : entity lcls_timing_core.GthRxAlignCheck
+   U_AlignCheck : entity surf.GtRxAlignCheck
       generic map (
-         TPD_G      => TPD_G,
-         GT_TYPE_G  => "GTHE3",
-         DRP_ADDR_G => AXI_CROSSBAR_MASTERS_CONFIG_C(1).baseAddr)
+         TPD_G          => TPD_G,
+         SIMULATION_G   => SIMULATION_G,
+         GT_TYPE_G      => "GTHE4",
+         AXI_CLK_FREQ_G => AXI_CLK_FREQ_G,
+         DRP_ADDR_G     => AXI_CROSSBAR_MASTERS_CONFIG_C(1).baseAddr)
       port map (
          -- Clock Monitoring
          txClk            => txoutclkb,
          rxClk            => rxoutclkb,
+         refClk           => axilClk,   -- Could probably also be stableClk
          -- GTH Status/Control Interface
          resetIn          => rxControl.reset,
          resetDone        => bypassdone,

diff --git a/LCLS-II/gthUltraScale/rtl/TimingGtCoreWrapper.vhd b/LCLS-II/gthUltraScale/rtl/TimingGtCoreWrapper.vhd
@@ -31,6 +31,7 @@ use unisim.vcomponents.all;
 entity TimingGtCoreWrapper is
    generic (
       TPD_G             : time    := 1 ns;
+      SIMULATION_G      : boolean := false;
       DISABLE_TIME_GT_G : boolean := false;
       EXTREF_G          : boolean := false;
       AXIL_BASE_ADDR_G  : slv(31 downto 0);
@@ -298,15 +299,18 @@ begin
          mAxiReadMasters     => axilReadMasters,
          mAxiReadSlaves      => axilReadSlaves);
 
-   U_AlignCheck : entity lcls_timing_core.GthRxAlignCheck
+   U_AlignCheck : entity surf.GtRxAlignCheck
       generic map (
-         TPD_G      => TPD_G,
-         GT_TYPE_G  => "GTHE3",
-         DRP_ADDR_G => AXI_CROSSBAR_MASTERS_CONFIG_C(1).baseAddr)
+         TPD_G          => TPD_G,
+         SIMULATION_G   => SIMULATION_G,
+         GT_TYPE_G      => "GTHE3",
+         AXI_CLK_FREQ_G => AXI_CLK_FREQ_G,
+         DRP_ADDR_G     => AXI_CROSSBAR_MASTERS_CONFIG_C(1).baseAddr)
       port map (
          -- Clock Monitoring
          txClk            => txoutclkb,
          rxClk            => rxoutclkb,
+         refClk           => axilClk,   -- Could probably also be stableClk
          -- GTH Status/Control Interface
          resetIn          => rxControl.reset,
          resetDone        => bypassdone,

diff --git a/LCLS-II/gtyUltraScale+/rtl/TimingGtCoreWrapper.vhd b/LCLS-II/gtyUltraScale+/rtl/TimingGtCoreWrapper.vhd
@@ -383,7 +383,7 @@ begin
       port map (
          -- Clock Monitoring
          txClk            => txoutclkb,
-         rxClk            => rxUsrClk,
+         rxClk            => rxoutclkb,
          refClk           => axilClk,   -- Could probably also be stableClk
          -- GTH Status/Control Interface
          resetIn          => rxControl.reset,