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Merge pull request #175 from slaclab/pre-release
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Release Candidate v3.8.4
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@ruck314
ruck314 authored Nov 14, 2024
2 parents 7875581 + 3cda340 commit 7ee3709
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Showing 8 changed files with 123 additions and 72 deletions.
1 change: 1 addition & 0 deletions LCLS-II/core/rtl/TimingGthWrapper.vhd
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Expand Up @@ -25,6 +25,7 @@ entity TimingGthWrapper is
TPD_G : time := 1 ns);

port (
-- StableClk (which is GT's drpClk) in the IP core configured for 156.25MHz/2 (78.125MHz)
stableClk : in sl;

gtRefClk : in sl;
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140 changes: 90 additions & 50 deletions LCLS-II/evr/rtl/EvrV2Trigger.vhd
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Expand Up @@ -45,26 +45,34 @@ entity EvrV2Trigger is
trigstate : out sl );
end EvrV2Trigger;

architecture EvrV2Trigger of EvrV2Trigger is
architecture rtl of EvrV2Trigger is

type PushState is (DISABLED_S, ENABLED_S, ARMED_S, PUSHING_S);

type RegType is record
fifo_delay : slv(TRIG_WIDTH_C-1 downto 0); -- clks until trigger fifo is empty
armed : sl;
delay : slv(TRIG_WIDTH_C-1 downto 0);
width : slv(TRIG_WIDTH_C-1 downto 0);
push_state : PushState;
duration : slv(TRIG_WIDTH_C-1 downto 0);
state : sl;
next_state : sl;
push_width : slv(TRIG_WIDTH_C-1 downto 0);
push_delay : slv(TRIG_WIDTH_C-1 downto 0);
skip : sl;
fifoReset : sl;
fifoWr : sl;
fifoRd : sl;
fifoDin : slv(TRIG_WIDTH_C-1 downto 0);
fifoDin : slv(TRIG_WIDTH_C downto 0);
end record;

constant REG_INIT_C : RegType := (
fifo_delay => (others=>'0'),
armed => '0',
delay => (others=>'0'),
width => (others=>'0'),
push_state => DISABLED_S,
duration => (others=>'0'),
state => '0',
next_state => '0',
push_width => (others=>'0'),
push_delay => (others=>'0'),
skip => '1',
fifoReset => '1',
fifoWr => '0',
fifoRd => '0',
Expand All @@ -77,11 +85,8 @@ architecture EvrV2Trigger of EvrV2Trigger is

signal fifoValid : sl;

signal fifoDout : slv(TRIG_WIDTH_C-1 downto 0);
signal fifoDout : slv(TRIG_WIDTH_C downto 0);
signal fifoCount : slv(FIFO_AWIDTH_C-1 downto 0);
signal fifoEmpty : sl;
signal fifoFull : sl;


signal fifoCountDbg : slv(6 downto 0);

Expand All @@ -90,75 +95,110 @@ begin
trigstate <= r.state;

GEN_NO_FIFO : if TRIG_DEPTH_C = 0 generate
fifoDout <= resize(config.delay,fifoDout'length);
fifoEmpty <= not r.fifoWr;
fifoDout <= r.fifoDin;
fifoValid <= r.fifoWr;
end generate;

GEN_FIFO : if TRIG_DEPTH_C > 0 generate
-- A fifo of delays before the next trigger edge
U_Fifo : entity surf.FifoSync
generic map ( TPD_G => TPD_G,
DATA_WIDTH_G => TRIG_WIDTH_C,
DATA_WIDTH_G => TRIG_WIDTH_C+1,
ADDR_WIDTH_G => FIFO_AWIDTH_C,
FWFT_EN_G => false )
FWFT_EN_G => true )
port map ( rst => r.fifoReset,
clk => clk,
wr_en => rin.fifoWr,
rd_en => rin.fifoRd,
din => rin.fifoDin,
dout => fifoDout,
valid => fifoValid,
empty => fifoEmpty,
full => fifoFull,
data_count => fifoCount );
end generate;

process (r, arm, fire, rst, config, fifoValid, fifoDout, fifoEmpty)
process (r, arm, fire, rst, config, fifoValid, fifoDout)
variable v : RegType;
variable x : slv(TRIG_WIDTH_C-1 downto 0);
begin
v := r;

v.state := not config.polarity;
v.fifoReset := '0';
v.fifoRd := '0';

if allBits(r.delay,'0') then
if allBits(r.width,'0') then
-- Trigger done. Wait for next fifo entry.
if r.fifoRd='1' then
v.width := config.width(TRIG_WIDTH_C-1 downto 0);
v.delay := fifoDout;
elsif fifoEmpty='0' then
v.fifoRd := '1';
v.fifoWr := '0';

if allBits(r.duration,'0') then
v.state := r.next_state;
-- Transition done. Wait for next fifo entry.
if fifoValid = '1' then
v.next_state := fifoDout(fifoDout'left);
x := fifoDout(fifoDout'left-1 downto 0);
if x = 0 then
v.state := v.next_state;
else
v.duration := x-1;
end if;
else
-- Delay complete. Assert trigger.
v.width := r.width-1;
v.state := config.polarity;
v.fifoRd := '1';
end if;
else
v.delay := r.delay-1;
v.duration := r.duration-1;
end if;

if fire = '1' and r.armed = '1' then
v.armed := '0';
-- Push the delay until trigger edge into the fifo
v.fifoWr := '1';
v.fifoDin := config.delay(TRIG_WIDTH_C-1 downto 0) - r.fifo_delay;
v.fifo_delay := config.delay(TRIG_WIDTH_C-1 downto 0) + config.width(TRIG_WIDTH_C-1 downto 0) + 1;
else
v.fifoWr := '0';
if not allBits(r.fifo_delay,'0') then
v.fifo_delay := r.fifo_delay - 1;
end if;
if not allBits(r.fifo_delay,'0') then
v.fifo_delay := r.fifo_delay - 1;
end if;

-- Trigger input logic
if ((arm(conv_integer(config.channel)) = '1' and not USE_MASK_G) or
((arm and config.channels(CHANNELS_C-1 downto 0)) /= toSlv(0,CHANNELS_C) and USE_MASK_G)) then
v.armed := '1';
-- Calculate the width push
x := config.width(TRIG_WIDTH_C-1 downto 0);
if config.delay(TRIG_WIDTH_C-1 downto 0) = 0 then
x := x-1;
end if;
v.push_width := x;

-- If the configured delay has been reduced such that this
-- trigger would precede one already in the fifo, eat it.
v.skip := '0';
if (r.fifo_delay+1 > config.delay(TRIG_WIDTH_C-1 downto 0) or
config.width(TRIG_WIDTH_C-1 downto 0) = 0) then
v.skip := '1';
end if;

-- Precalculate
v.push_delay := config.delay(TRIG_WIDTH_C-1 downto 0) + config.width(TRIG_WIDTH_C-1 downto 0) - 1;

case r.push_state is
when DISABLED_S =>
if config.enabled = '1' then
-- set the polarity
v.push_state := ENABLED_S;
v.fifoWr := '1';
v.fifoDin := not config.polarity & toSlv(0,TRIG_WIDTH_C);
end if;
when ENABLED_S =>
-- Trigger input logic
if ((arm(conv_integer(config.channel)) = '1' and not USE_MASK_G) or
((arm and config.channels(CHANNELS_C-1 downto 0)) /= toSlv(0,CHANNELS_C) and USE_MASK_G)) then
v.push_state := ARMED_S;
end if;
when ARMED_S =>
if fire = '1' then
if r.skip = '1' then
v.push_state := ENABLED_S;
else
-- Push the delay until trigger edge into the fifo
v.push_state := PUSHING_S;
v.fifoWr := '1';
v.fifoDin := config.polarity & (config.delay(TRIG_WIDTH_C-1 downto 0) - r.fifo_delay);
v.fifo_delay := r.push_delay;
end if;
end if;
when PUSHING_S =>
-- Push the width into the fifo
v.fifoWr := '1';
v.fifoDin := not config.polarity & r.push_width;
v.push_state := ENABLED_S;
when others => NULL;
end case;

if rst='1' or config.enabled='0' then
v := REG_INIT_C;
end if;
Expand All @@ -173,5 +213,5 @@ begin
end if;
end process;

end EvrV2Trigger;
end rtl;

2 changes: 1 addition & 1 deletion LCLS-II/gthUltraScale+/rtl/TimingGthCoreWrapper.vhd
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Expand Up @@ -44,7 +44,7 @@ entity TimingGthCoreWrapper is
axilReadSlave : out AxiLiteReadSlaveType;
axilWriteMaster : in AxiLiteWriteMasterType;
axilWriteSlave : out AxiLiteWriteSlaveType;

-- StableClk (which is GT's drpClk) in the IP core configured for 156.25MHz/2 (78.125MHz)
stableClk : in sl; -- Unused in GTHE3, but used in GTHE4/GTYE4
stableRst : in sl; -- Unused in GTHE3, but used in GTHE4/GTYE4
-- GTH FPGA IO
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12 changes: 7 additions & 5 deletions LCLS-II/gthUltraScale+/ruckus.tcl
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Expand Up @@ -4,11 +4,13 @@ source -quiet $::env(RUCKUS_DIR)/vivado_proc.tcl
if { $::env(VIVADO_VERSION) >= 2022.2} {
loadSource -lib lcls_timing_core -dir "$::DIR_PATH/rtl"

loadSource -lib lcls_timing_core -path "$::DIR_PATH/coregen/TimingGth_extref.dcp"
#loadIpCore -path "$::DIR_PATH/coregen/TimingGth_extref.xci"

loadSource -lib lcls_timing_core -path "$::DIR_PATH/coregen/TimingGth_fixedlat.dcp"
#loadIpCore -path "$::DIR_PATH/coregen/TimingGth_fixedlat.xci"
if { [info exists ::env(LCLS_TIMING_XCI)] != 0 && $::env(LCLS_TIMING_XCI) == 1 } {
loadIpCore -path "$::DIR_PATH/coregen/TimingGth_extref.xci"
loadIpCore -path "$::DIR_PATH/coregen/TimingGth_fixedlat.xci"
} else {
loadSource -lib lcls_timing_core -path "$::DIR_PATH/coregen/TimingGth_extref.dcp"
loadSource -lib lcls_timing_core -path "$::DIR_PATH/coregen/TimingGth_fixedlat.dcp"
}
} else {
puts "\n\nWARNING: $::DIR_PATH requires Vivado 2022.2 (or later)\n\n"
}
2 changes: 1 addition & 1 deletion LCLS-II/gthUltraScale/rtl/TimingGtCoreWrapper.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -44,7 +44,7 @@ entity TimingGtCoreWrapper is
axilReadSlave : out AxiLiteReadSlaveType;
axilWriteMaster : in AxiLiteWriteMasterType;
axilWriteSlave : out AxiLiteWriteSlaveType;

-- StableClk (which is GT's drpClk) in the IP core configured for 156.25MHz/2 (78.125MHz)
stableClk : in sl; -- Unused in GTHE3, but used in GTHE4/GTYE4
stableRst : in sl; -- Unused in GTHE3, but used in GTHE4/GTYE4
-- GTH FPGA IO
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12 changes: 7 additions & 5 deletions LCLS-II/gthUltraScale/ruckus.tcl
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Expand Up @@ -5,11 +5,13 @@ if { $::env(VIVADO_VERSION) >= 2016.4 } {

loadSource -lib lcls_timing_core -dir "$::DIR_PATH/rtl"

loadSource -lib lcls_timing_core -path "$::DIR_PATH/coregen/TimingGth_extref.dcp"
# loadIpCore -path "$::DIR_PATH/coregen/TimingGth_extref.xci"

loadSource -lib lcls_timing_core -path "$::DIR_PATH/coregen/TimingGth_fixedlat.dcp"
# loadIpCore -path "$::DIR_PATH/coregen/TimingGth_fixedlat.xci"
if { [info exists ::env(LCLS_TIMING_XCI)] != 0 && $::env(LCLS_TIMING_XCI) == 1 } {
loadIpCore -path "$::DIR_PATH/coregen/TimingGth_extref.xci"
loadIpCore -path "$::DIR_PATH/coregen/TimingGth_fixedlat.xci"
} else {
loadSource -lib lcls_timing_core -path "$::DIR_PATH/coregen/TimingGth_extref.dcp"
loadSource -lib lcls_timing_core -path "$::DIR_PATH/coregen/TimingGth_fixedlat.dcp"
}

} else {
puts "\n\nWARNING: $::DIR_PATH requires Vivado 2016.4 (or later)\n\n"
Expand Down
2 changes: 1 addition & 1 deletion LCLS-II/gtyUltraScale+/rtl/TimingGtCoreWrapper.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -44,7 +44,7 @@ entity TimingGtCoreWrapper is
axilReadSlave : out AxiLiteReadSlaveType;
axilWriteMaster : in AxiLiteWriteMasterType;
axilWriteSlave : out AxiLiteWriteSlaveType;

-- StableClk (which is GT's drpClk) in the IP core configured for 156.25MHz/2 (78.125MHz)
stableClk : in sl; -- Unused in GTHE3, but used in GTHE4/GTYE4
stableRst : in sl; -- Unused in GTHE3, but used in GTHE4/GTYE4
-- GTY FPGA IO
Expand Down
24 changes: 15 additions & 9 deletions LCLS-II/gtyUltraScale+/ruckus.tcl
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Expand Up @@ -14,19 +14,25 @@ if { [info exists ::env(TIMING_246MHz)] != 1 || $::env(TIMING_246MHz) == 0 } {

if { $::env(VIVADO_VERSION) >= 2021.1 && [info exists ::env(TIMING_246MHz)] != 1} {

loadSource -lib lcls_timing_core -path "${path}/TimingGty_extref.dcp"
# loadIpCore -path "${path}/TimingGty_extref.xci"
if { [info exists ::env(LCLS_TIMING_XCI)] != 0 && $::env(LCLS_TIMING_XCI) == 1 } {
loadIpCore -path "${path}/TimingGty_extref.xci"
loadIpCore -path "${path}/TimingGty_fixedlat.xci"
puts "Loading XCI files for LCLS Timing"
} else {
loadSource -lib lcls_timing_core -path "${path}/TimingGty_extref.dcp"
loadSource -lib lcls_timing_core -path "${path}/TimingGty_fixedlat.dcp"
}

loadSource -lib lcls_timing_core -path "${path}/TimingGty_fixedlat.dcp"
# loadIpCore -path "${path}/TimingGty_fixedlat.xci"

} elseif { $::env(VIVADO_VERSION) >= 2020.2 && [info exists ::env(TIMING_246MHz)] == 1 } {

loadSource -lib lcls_timing_core -path "${path}/TimingGty_extref.dcp"
# loadIpCore -path "${path}/TimingGty_extref.xci"

loadSource -lib lcls_timing_core -path "${path}/TimingGty_fixedlat.dcp"
# loadIpCore -path "${path}/TimingGty_fixedlat.xci"
if { [info exists ::env(LCLS_TIMING_XCI)] != 0 && $::env(LCLS_TIMING_XCI) == 1 } {
loadIpCore -path "${path}/TimingGty_extref.xci"
loadIpCore -path "${path}/TimingGty_fixedlat.xci"
} else {
loadSource -lib lcls_timing_core -path "${path}/TimingGty_extref.dcp"
loadSource -lib lcls_timing_core -path "${path}/TimingGty_fixedlat.dcp"
}

} else {
puts "\n\nWARNING: $::DIR_PATH requires Vivado 2021.1 (or later)\n\n"
Expand Down

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