This is the VHDL description of the DRRA and DiMArch CGRA fabric developed by KTH.
The VHDL code, the logic and concepts described in this file constitute the intellectual property of the authors listed below, who are affiliated to KTH(Kungliga Tekniska Högskolan), School of ICT, Kista. Any unauthorised use, copy or distribution is strictly prohibited. Any authorised use, copy or distribution should carry this copyright notice unaltered.
Contact :
- Dimitrios Stathis [email protected]
- Yu Yang [email protected]
For documentation see: https://github.com/silagokth/SiLagoDoc
SiLago is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
SiLago is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with SiLago, see LICENSE file. If not, see https://www.gnu.org/licenses/.