clarify CSRs which are only added if hybrid mode is implemented

[tariqkurd-repo]

No description provided.

[arichardson]

I am not sure if we do need both mscratchc and mtdc for purecap. Maybe @nwf / @davidchisnall can comment on whether Cheriot needs both.

[jrtc27]

I am not sure if we do need both mscratchc and mtdc for purecap. Maybe @nwf / @davidchisnall can comment on whether Cheriot needs both.

https://github.com/CHERIoT-Platform/cheriot-rtos/blob/883d2cc85032e01b7eb8e7a4bb31e6764227677a/sdk/include/cheri.hh#L1395-L1396

So looks to be obsoleted by xtidc.

[arichardson]

I am not sure if we do need both mscratchc and mtdc for purecap. Maybe @nwf / @davidchisnall can comment on whether Cheriot needs both.

https://github.com/CHERIoT-Platform/cheriot-rtos/blob/883d2cc85032e01b7eb8e7a4bb31e6764227677a/sdk/include/cheri.hh#L1395-L1396

So looks to be obsoleted by xtidc.

Ah yes if we have the tidc registers this should not be needed. I personally still think it would be cleaner to have a per-ring DDC so you don't need to switch manually but I don't think we can change that easily.

[jrtc27]

I am not sure if we do need both mscratchc and mtdc for purecap. Maybe @nwf / @davidchisnall can comment on whether Cheriot needs both.

https://github.com/CHERIoT-Platform/cheriot-rtos/blob/883d2cc85032e01b7eb8e7a4bb31e6764227677a/sdk/include/cheri.hh#L1395-L1396
So looks to be obsoleted by xtidc.

Ah yes if we have the tidc registers this should not be needed. I personally still think it would be cleaner to have a per-ring DDC so you don't need to switch manually but I don't think we can change that easily.

I agree that would be nicer, but doing it the RISC-V way would then likely be ddc + xtdc + xedc, as it mostly doesn't bank registers (with the exception of some hypervisor ones).

[tariqkurd-repo]

I am not sure if we do need both mscratchc and mtdc for purecap. Maybe @nwf / @davidchisnall can comment on whether Cheriot needs both.

https://github.com/CHERIoT-Platform/cheriot-rtos/blob/883d2cc85032e01b7eb8e7a4bb31e6764227677a/sdk/include/cheri.hh#L1395-L1396
So looks to be obsoleted by xtidc.

Ah yes if we have the tidc registers this should not be needed. I personally still think it would be cleaner to have a per-ring DDC so you don't need to switch manually but I don't think we can change that easily.

I agree that would be nicer, but doing it the RISC-V way would then likely be ddc + xtdc + xedc, as it mostly doesn't bank registers (with the exception of some hypervisor ones).

ok - so are there any suggested changes to this PR - or are we happy that it's correct (or at least good enough for now?)
this was my understanding of CSRs added by implementing Zcherihybrid so it's good to cross-check that with other people's understanding.