Mark c0-authorized loads and stores as extensible (#403)

Say explicitly that `c0`-authorized load/store instructions, which are guaranteed to trap regardless of other operands' values, are available for use by future extensions. --------- Signed-off-by: Tariq Kurd <[email protected]> Signed-off-by: Tariq Kurd <[email protected]> Co-authored-by: Tariq Kurd <[email protected]> Co-authored-by: Alexander Richardson <[email protected]> Co-authored-by: Tariq Kurd <[email protected]>
riscv · Oct 15, 2024 · cf7e656 · cf7e656
1 parent 9f17dee
commit cf7e656
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diff --git a/src/insns/amo_32bit.adoc b/src/insns/amo_32bit.adoc
@@ -30,6 +30,8 @@ include::wavedrom/amo.adoc[]
 
 {cheri_cap_mode_name} Description::
 Standard atomic instructions, authorised by the capability in `cs1`.
++
+include::load_store_c0.adoc[]
 
 {cheri_int_mode_name} Description::
 Standard atomic instructions, authorised by the capability in <<ddc>>.

diff --git a/src/insns/amoswap_32bit_cap.adoc b/src/insns/amoswap_32bit_cap.adoc
@@ -17,6 +17,8 @@ include::wavedrom/amoswap_cap.adoc[]
 
 {cheri_cap_mode_name} Description::
 Atomic swap of capability type, authorised by the capability in `cs1`.
++
+include::load_store_c0.adoc[]
 
 {cheri_int_mode_name} Description::
 Atomic swap of capability type, authorised by the capability in <<ddc>>.

diff --git a/src/insns/hypv-virt-load-cap.adoc b/src/insns/hypv-virt-load-cap.adoc
@@ -21,6 +21,8 @@ translation and protection, and endianness, that apply to memory accesses in
 either VS-mode or VU-mode. The effective address is the address of `cs1`. The
 authorising capability for the operation is `cs1`. A copy of the loaded value
 is written to `cd`.
++
+include::load_store_c0.adoc[]
 
 {cheri_int_mode_name} Description::
 Load a CLEN+1 bit value from memory as though V=1; i.e., with the address

diff --git a/src/insns/hypv-virt-load.adoc b/src/insns/hypv-virt-load.adoc
@@ -69,6 +69,8 @@ protection, and endianness, that apply to memory accesses in either VS-mode or
 VU-mode. The effective address is the address of `cs1`. The authorising
 capability for the operation is `cs1`. A copy of the loaded value is written to
 `rd`.
++
+include::load_store_c0.adoc[]
 
 {cheri_int_mode_name} Description::
 Performs a load as though V=1; i.e., with the address translation and

diff --git a/src/insns/hypv-virt-loadx.adoc b/src/insns/hypv-virt-loadx.adoc
@@ -29,6 +29,8 @@ translation and protection, and endianness, that apply to memory access in
 either VS-mode or VU-mode. The effective address is the address of `cs1`. The
 authorising capability for the operation is `cs1`. A copy of the loaded value
 is written to `rd`.
++
+include::load_store_c0.adoc[]
 
 {cheri_int_mode_name} Description::
 Performs a load with the *execute* permission taking the place of *read*

diff --git a/src/insns/hypv-virt-store-cap.adoc b/src/insns/hypv-virt-store-cap.adoc
@@ -20,6 +20,8 @@ Store a CLEN+1 bit value in `cs2` to memory as though V=1; i.e., with the
 address translation and protection, and endianness, that apply to memory
 accesses in either VS-mode or VU-mode. The effective address is the address of
 `cs1`. The authorising capability for the operation is `cs1`.
++
+include::load_store_c0.adoc[]
 
 {cheri_int_mode_name} Description::
 Store a CLEN+1 bit value in `cs2` to memory as though V=1; i.e., with the

diff --git a/src/insns/hypv-virt-store.adoc b/src/insns/hypv-virt-store.adoc
@@ -55,6 +55,8 @@ VU-mode. The effective address is the address of `cs1`. The authorising
 capability for the operation is `cs1`. A copy of `rs2` is written to memory at
 the location indicated by the effective address and the tag bit of each block
 of memory naturally aligned to CLEN/8 is cleared.
++
+include::load_store_c0.adoc[]
 
 {cheri_int_mode_name} Description::
 Performs a store as though V=1; i.e., with address translation and protection,

diff --git a/src/insns/load_32bit.adoc b/src/insns/load_32bit.adoc
@@ -68,6 +68,8 @@ Load integer data of the indicated size (byte, halfword, word, double-word)
 from memory. The effective address of the load is obtained by adding the
 sign-extended 12-bit offset to the address of `cs1`. The authorising capability
 for the operation is `cs1`. A copy of the loaded value is written to `rd`.
++
+include::load_store_c0.adoc[]
 
 {cheri_int_mode_name} Description::
 Load integer data of the indicated size (byte, halfword, word, double-word)

diff --git a/src/insns/load_32bit_cap.adoc b/src/insns/load_32bit_cap.adoc
@@ -21,6 +21,8 @@ include::wavedrom/loadcap.adoc[]
 
 {cheri_cap_mode_name} Description::
 Load a CLEN+1 bit value from memory and writes it to `cd`. The capability in `cs1` authorizes the operation. The effective address of the memory access is obtained by adding the address of `cs1` to the sign-extended 12-bit offset.
++
+include::load_store_c0.adoc[]
 
 {cheri_int_mode_name} Description::
 Loads a CLEN+1 bit value from memory and writes it to `cd`. The capability

diff --git a/src/insns/load_32bit_fp.adoc b/src/insns/load_32bit_fp.adoc
@@ -31,6 +31,8 @@ include::wavedrom/fpload.adoc[]
 
 {cheri_cap_mode_name} Description::
 Standard floating point load instructions, authorised by the capability in `cs1`.
++
+include::load_store_c0.adoc[]
 
 {cheri_int_mode_name} Description::
 Standard floating point load instructions, authorised by the capability in <<ddc>>.

diff --git a/src/insns/load_res_32bit.adoc b/src/insns/load_res_32bit.adoc
@@ -37,6 +37,8 @@ include::wavedrom/load_res.adoc[]
 
 {cheri_cap_mode_name} Description::
 Load reserved instructions, authorised by the capability in `cs1`.
++
+include::load_store_c0.adoc[]
 
 {cheri_int_mode_name} Description::
 Load reserved instructions, authorised by the capability in <<ddc>>.

diff --git a/src/insns/load_res_cap_32bit.adoc b/src/insns/load_res_cap_32bit.adoc
@@ -18,6 +18,8 @@ include::wavedrom/load_res_cap.adoc[]
 {cheri_cap_mode_name} Description::
 Load reserved instructions, authorised by the capability in `cs1`.
  All misaligned load reservations cause a load address misaligned exception to allow software emulation (Zam extension, see cite:[riscv-unpriv-spec]).
++
+include::load_store_c0.adoc[]
 
 {cheri_int_mode_name} Description::
 Load reserved instructions, authorised by the capability in <<ddc>>.

diff --git a/src/insns/load_store_c0.adoc b/src/insns/load_store_c0.adoc
@@ -0,0 +1,2 @@
+NOTE: Any instance of this instruction with a `cs1` of `c0` would certainly trap (with a CHERI tag violation), as `c0` is defined to always hold a <<null-cap>> capability.
+As such, the encodings with a `cs1` of `c0` are RESERVED for use by future extensions.
diff --git a/src/insns/store_32bit.adoc b/src/insns/store_32bit.adoc
@@ -55,6 +55,8 @@ sign-extended 12-bit offset to the address of `cs1`. The authorising capability
 for the operation is `cs1`. A copy of `rs2` is written to memory at the
 location indicated by the effective address and the tag bit of each block of
 memory naturally aligned to CLEN/8 is cleared.
++
+include::load_store_c0.adoc[]
 
 {cheri_int_mode_name} Description::
 Store integer data of the indicated size (byte, halfword, word, double-word) to

diff --git a/src/insns/store_32bit_cap.adoc b/src/insns/store_32bit_cap.adoc
@@ -21,6 +21,8 @@ include::wavedrom/storecap.adoc[]
 Store the CLEN+1 bit value in `cs2` to memory. The capability in `cs1`
 authorizes the operation. The effective address of the memory access is
 obtained by adding the address of `cs1` to the sign-extended 12-bit offset.
++
+include::load_store_c0.adoc[]
 
 {cheri_int_mode_name} Description::
 Store the CLEN+1 bit value in `cs2` to memory. The capability

diff --git a/src/insns/store_32bit_fp.adoc b/src/insns/store_32bit_fp.adoc
@@ -31,6 +31,8 @@ include::wavedrom/fpstore.adoc[]
 
 {cheri_cap_mode_name} Description::
 Standard floating point store instructions, authorised by the capability in `cs1`.
++
+include::load_store_c0.adoc[]
 
 {cheri_int_mode_name} Description::
 Standard floating point store instructions, authorised by the capability in <<ddc>>.

diff --git a/src/insns/store_cond_32bit.adoc b/src/insns/store_cond_32bit.adoc
@@ -37,6 +37,8 @@ include::wavedrom/store_cond.adoc[]
 
 {cheri_cap_mode_name} Description::
 Store conditional instructions, authorised by the capability in `cs1`.
++
+include::load_store_c0.adoc[]
 
 {cheri_int_mode_name} Description::
 Store conditional instructions, authorised by the capability in <<ddc>>.

diff --git a/src/insns/store_cond_cap_32bit.adoc b/src/insns/store_cond_cap_32bit.adoc
@@ -18,6 +18,8 @@ include::wavedrom/store_cond_cap.adoc[]
 {cheri_cap_mode_name} Description::
 Store conditional instructions, authorised by the capability in `cs1`.
  All misaligned store conditionals cause a store/AMO address misaligned exception to allow software emulation (Zam extension, see cite:[riscv-unpriv-spec]).
++
+include::load_store_c0.adoc[]
 
 {cheri_int_mode_name} Description::
 Store conditional instructions, authorised by the capability in <<ddc>>.

diff --git a/src/insns/wavedrom/amo.adoc b/src/insns/wavedrom/amo.adoc
@@ -6,7 +6,7 @@
   {bits: 7,  name: 'opcode',   attr: ['7', 'AMO=0101111'], type: 8},
   {bits: 5,  name: 'rd',       attr: ['5', 'rdest[4:0]'], type: 3},
   {bits: 3,  name: 'funct3',   attr: ['3', '.W=010', 'rv64: .D=011'], type: 8},
-  {bits: 5,  name: 'rs1',      attr: ['5', 'base'], type: 4},
+  {bits: 5,  name: 'rs1/cs1!=0',attr: ['5', 'base'], type: 4},
   {bits: 5,  name: 'rs2',      attr: ['5', 'src'],  type: 4},
   {bits: 1,  name: 'rl',       attr: ['1', 'rl'],  type: 4},
   {bits: 1,  name: 'aq',       attr: ['1', 'aq'],  type: 4},

diff --git a/src/insns/wavedrom/amoswap_cap.adoc b/src/insns/wavedrom/amoswap_cap.adoc
@@ -6,7 +6,7 @@
   {bits: 7,  name: 'opcode',   attr: ['7', 'AMO=0101111'], type: 8},
   {bits: 5,  name: 'cd',       attr: ['5', 'rdest[4:0]'], type: 3},
   {bits: 3,  name: 'funct3',   attr: ['3', 'width', '.C=100'], type: 8},
-  {bits: 5,  name: 'cs1',      attr: ['5', 'base'], type: 4},
+  {bits: 5,  name: 'cs1!=0',   attr: ['5', 'base'], type: 4},
   {bits: 5,  name: 'cs2',      attr: ['5', 'src'],  type: 4},
   {bits: 1,  name: 'rl',       attr: ['1', 'rl'],  type: 4},
   {bits: 1,  name: 'aq',       attr: ['1', 'aq'],  type: 4},

diff --git a/src/insns/wavedrom/fpload.adoc b/src/insns/wavedrom/fpload.adoc
@@ -5,7 +5,7 @@
   {bits: 7,  name: 'opcode',    attr: ['7','LOAD-FP=0000111'],  type: 8},
   {bits: 5,  name: 'rd',        attr: ['5','dest'],     type: 2},
   {bits: 3,  name: 'width',     attr: ['3','FLD=011','FLW=010', 'FLH=001'],    type: 8},
-  {bits: 5,  name: 'rs1/cs1',   attr: ['5','base'],     type: 4},
+  {bits: 5,  name: 'rs1/cs1!=0',attr: ['5','base'],     type: 4},
   {bits: 12, name: 'imm[11:0]', attr: ['12','offset[11:0]'],   type: 3},
 ]}
 ....
diff --git a/src/insns/wavedrom/fpstore.adoc b/src/insns/wavedrom/fpstore.adoc
@@ -5,7 +5,7 @@
   {bits: 7,  name: 'opcode',    attr: ['7','STORE-FP=0100111'], type: 8},
   {bits: 5,  name: 'imm[4:0]',  attr: ['5','offset[4:0]'],   type: 3},
   {bits: 3,  name: 'width',     attr: ['3','FSD=011','FSW=010', 'FSH=001'],    type: 8},
-  {bits: 5,  name: 'rs1/cs1',   attr: ['5','base'],     type: 4},
+  {bits: 5,  name: 'rs1/cs1!=0',attr: ['5','base'],     type: 4},
   {bits: 5,  name: 'rs2',       attr: ['5','src'],      type: 4},
   {bits: 7,  name: 'imm[11:5]', attr: ['7','offset[11:5]'],   type: 3},
 ]}

diff --git a/src/insns/wavedrom/hypv-virt-load-cap.adoc b/src/insns/wavedrom/hypv-virt-load-cap.adoc
@@ -4,7 +4,7 @@
   {bits: 7,  name: 0x73,      attr: ['7'], type: 8},
   {bits: 5,  name: 'cd',      attr: ['5'], type: 2},
   {bits: 3,  name: 0x4,       attr: ['3'], type: 8},
-  {bits: 5,  name: 'rs1/cs1', attr: ['5', 'src1'], type: 4},
+  {bits: 5,  name: 'rs1/cs1!=0',attr: ['5', 'src1'], type: 4},
   {bits: 5,  name: 'type',    attr: ['5', 'HLV.C=00000'], type: 3},
   {bits: 7,  name: 'funct7',  attr: ['7', 'HLV.C=0111000'], type: 3},
 ]}

diff --git a/src/insns/wavedrom/hypv-virt-load.adoc b/src/insns/wavedrom/hypv-virt-load.adoc
@@ -4,7 +4,7 @@
   {bits: 7,  name: 0x73,      attr: ['7'], type: 8},
   {bits: 5,  name: 'rd',      attr: ['5'], type: 2},
   {bits: 3,  name: 0x4,       attr: ['3'], type: 8},
-  {bits: 5,  name: 'rs1/cs1', attr: ['5', 'src1'], type: 4},
+  {bits: 5,  name: 'rs1/cs1!=0',attr: ['5', 'src1'], type: 4},
   {bits: 5,  name: 'type',    attr: ['5', 'HLV.B=00000', 'HLV.BU=00001', 'HLV.H=00000', 'HLV.HU=00001', 'HLV.W=00000', 'HLV.WU=00001', 'HLV.D=00000'], type: 3},
   {bits: 7,  name: 'funct7',  attr: ['7', 'HLV.B=0110000', 'HLV.BU=0110000', 'HLV.H=0110010', 'HLV.HU=0110010', 'HLV.W=0110100', 'HLV.WU=0110100', 'HLV.D=0110110'], type: 3},
 ]}

diff --git a/src/insns/wavedrom/hypv-virt-loadx.adoc b/src/insns/wavedrom/hypv-virt-loadx.adoc
@@ -4,7 +4,7 @@
   {bits: 7,  name: 0x73,      attr: ['7'], type: 8},
   {bits: 5,  name: 'rd',      attr: ['5', 'dest'], type: 2},
   {bits: 3,  name: 0x4,       attr: ['3'], type: 8},
-  {bits: 5,  name: 'rs1/cs1', attr: ['5', 'src1'], type: 4},
+  {bits: 5,  name: 'rs1/cs1!=0',attr: ['5', 'src1'], type: 4},
   {bits: 5,  name: 0x3,       attr: ['5'], type: 3},
   {bits: 7,  name: 'funct7',  attr: ['7', 'HLVX.HU=0110010', 'HLVX.WU=0110100'], type: 3},
 ]}

diff --git a/src/insns/wavedrom/hypv-virt-store-cap.adoc b/src/insns/wavedrom/hypv-virt-store-cap.adoc
@@ -4,7 +4,7 @@
   {bits: 7,  name: 0x73,      attr: ['7'], type: 8},
   {bits: 5,  name: 0x0,       attr: ['5'], type: 2},
   {bits: 3,  name: 0x4,       attr: ['3'], type: 8},
-  {bits: 5,  name: 'rs1/cs1', attr: ['5', 'src1'], type: 4},
+  {bits: 5,  name: 'rs1/cs1!=0',attr: ['5', 'src1'], type: 4},
   {bits: 5,  name: 'cs2',     attr: ['5', 'src2'], type: 3},
   {bits: 7,  name: 'funct7',  attr: ['7', 'HSV.C=0111001'], type: 3},
 ]}

diff --git a/src/insns/wavedrom/hypv-virt-store.adoc b/src/insns/wavedrom/hypv-virt-store.adoc
@@ -4,7 +4,7 @@
   {bits: 7,  name: 0x73,      attr: ['7'], type: 8},
   {bits: 5,  name: 0x0,       attr: ['5'], type: 2},
   {bits: 3,  name: 0x4,       attr: ['3'], type: 8},
-  {bits: 5,  name: 'rs1/cs1', attr: ['5', 'src1'], type: 4},
+  {bits: 5,  name: 'rs1/cs1!=0',attr: ['5', 'src1'], type: 4},
   {bits: 5,  name: 'rs2',     attr: ['5', 'src2'], type: 3},
   {bits: 7,  name: 'funct7',  attr: ['7', 'HSV.B=0110001', 'HSV.H=0110011', 'HSV.W=0110101', 'HSV.D=0110111'], type: 3},
 ]}

diff --git a/src/insns/wavedrom/load.adoc b/src/insns/wavedrom/load.adoc
@@ -6,7 +6,7 @@
   {bits: 7,  name: 'opcode',    attr: ['7', 'LOAD=0000011'], type: 8},
   {bits: 5,  name: 'rd',        attr: ['5', 'dest'], type: 2},
   {bits: 3,  name: 'funct3',    attr: ['3', 'width', 'LB=000', 'LH=001', 'LW=010', 'LBU=100', 'LHU=101', 'rv64: LWU=110', 'rv64: LD=011'], type: 8},
-  {bits: 5,  name: 'rs1/cs1',   attr: ['5', 'base'], type: 4},
+  {bits: 5,  name: 'rs1/cs1!=0',attr: ['5', 'base'], type: 4},
   {bits: 12, name: 'imm[11:0]', attr: ['12', 'offset[11:0]'], type: 3},
 ]}
 ....
diff --git a/src/insns/wavedrom/load_res.adoc b/src/insns/wavedrom/load_res.adoc
@@ -6,7 +6,7 @@
   {bits: 7,  name: 'opcode',   attr: ['7', 'AMO=0101111'], type: 8},
   {bits: 5,  name: 'rd',       attr: ['5', 'rdest[4:0]'], type: 3},
   {bits: 3,  name: 'funct3',   attr: ['3', '.B=000', '.H=001', '.W=010', 'rv64: .D=011'], type: 8},
-  {bits: 5,  name: 'rs1',      attr: ['5', 'base'], type: 4},
+  {bits: 5,  name: 'rs1/cs1!=0',attr: ['5', 'base'], type: 4},
   {bits: 5,  name: 'rs2',      attr: ['5', 'LR.*=00000'],  type: 4},
   {bits: 1,  name: 'rl',       attr: ['1', 'rl'],  type: 4},
   {bits: 1,  name: 'aq',       attr: ['1', 'aq'],  type: 4},

diff --git a/src/insns/wavedrom/load_res_cap.adoc b/src/insns/wavedrom/load_res_cap.adoc
@@ -6,7 +6,7 @@
   {bits: 7,  name: 'opcode',   attr: ['7', 'AMO=0101111'], type: 8},
   {bits: 5,  name: 'cd',       attr: ['5', 'rdest[4:0]'], type: 3},
   {bits: 3,  name: 'funct3',   attr: ['3', '.C=100'], type: 8},
-  {bits: 5,  name: 'cs1/rs1',  attr: ['5', 'base'], type: 4},
+  {bits: 5,  name: 'rs1/cs1!=0',attr: ['5', 'base'], type: 4},
   {bits: 5,  name: 'funct5',   attr: ['5', 'LR.*=00000'],  type: 4},
   {bits: 1,  name: 'rl',       attr: ['1', 'rl'],  type: 4},
   {bits: 1,  name: 'aq',       attr: ['1', 'aq'],  type: 4},

diff --git a/src/insns/wavedrom/loadcap.adoc b/src/insns/wavedrom/loadcap.adoc
@@ -6,7 +6,7 @@
   {bits: 7,  name: 'opcode',    attr: ['7', 'MISCMEM=0001111'], type: 8},
   {bits: 5,  name: 'cd',        attr: ['5', 'dest'], type: 2},
   {bits: 3,  name: 'funct3',    attr: ['3', 'LC=100'], type: 8},
-  {bits: 5,  name: 'rs1/cs1',   attr: ['5', 'base'], type: 4},
+  {bits: 5,  name: 'rs1/cs1!=0',attr: ['5', 'base'], type: 4},
   {bits: 12, name: 'imm[11:0]', attr: ['12', 'offset[11:0]'], type: 3},
 ]}
 ....
diff --git a/src/insns/wavedrom/store.adoc b/src/insns/wavedrom/store.adoc
@@ -6,7 +6,7 @@
   {bits: 7,  name: 'opcode',   attr: ['7', 'STORE=0100011'], type: 8},
   {bits: 5,  name: 'imm[4:0]', attr: ['5', 'offset[4:0]'], type: 3},
   {bits: 3,  name: 'funct3', attr: ['3', 'SB=000','SH=001','SW=010','rv64: SD=011'], type: 8},
-  {bits: 5,  name: 'rs1/cs1', attr: ['5', 'base'], type: 4},
+  {bits: 5,  name: 'rs1/cs1!=0', attr: ['5', 'base'], type: 4},
   {bits: 5,  name: 'rs2', attr: ['5', 'src'], type: 4},
   {bits: 7, name: 'imm[11:5]', attr: ['7', 'offset[11:5]'], type: 3},
 ]}

diff --git a/src/insns/wavedrom/store_cond.adoc b/src/insns/wavedrom/store_cond.adoc
@@ -6,7 +6,7 @@
   {bits: 7,  name: 'opcode',   attr: ['7', 'AMO=0101111'], type: 8},
   {bits: 5,  name: 'rd',       attr: ['5', 'rdest[4:0]'], type: 3},
   {bits: 3,  name: 'funct3',   attr: ['3', 'width', '.B=000','.H=001','.W=010', 'rv64: .D=011'], type: 8},
-  {bits: 5,  name: 'rs1',      attr: ['5', 'base'], type: 4},
+  {bits: 5,  name: 'rs1/cs1!=0',attr: ['5', 'base'], type: 4},
   {bits: 5,  name: 'rs2',      attr: ['5', 'src'],  type: 4},
   {bits: 1,  name: 'rl',       attr: ['1', 'rl'],  type: 4},
   {bits: 1,  name: 'aq',       attr: ['1', 'aq'],  type: 4},

diff --git a/src/insns/wavedrom/store_cond_cap.adoc b/src/insns/wavedrom/store_cond_cap.adoc
@@ -6,7 +6,7 @@
   {bits: 7,  name: 'opcode',   attr: ['7', 'AMO=0101111'], type: 8},
   {bits: 5,  name: 'rd',       attr: ['5', 'rdest[4:0]'], type: 3},
   {bits: 3,  name: 'funct3',   attr: ['3', 'width', '.C=100'], type: 8},
-  {bits: 5,  name: 'cs1/rs1',  attr: ['5', 'base'], type: 4},
+  {bits: 5,  name: 'rs1/cs1!=0',attr: ['5', 'base'], type: 4},
   {bits: 5,  name: 'cs2',      attr: ['5', 'src'],  type: 4},
   {bits: 1,  name: 'rl',       attr: ['1', 'rl'],  type: 4},
   {bits: 1,  name: 'aq',       attr: ['1', 'aq'],  type: 4},

diff --git a/src/insns/wavedrom/storecap.adoc b/src/insns/wavedrom/storecap.adoc
@@ -6,7 +6,7 @@
   {bits: 7,  name: 'opcode',    attr: ['7', 'STORE=0100011'], type: 8},
   {bits: 5,  name: 'imm[4:0]',  attr: ['5', 'offset[4:0]'], type: 3},
   {bits: 3,  name: 'funct3',    attr: ['3', 'SC=100'], type: 8},
-  {bits: 5,  name: 'rs1/cs1',   attr: ['5', 'base'], type: 4},
+  {bits: 5,  name: 'rs1/cs1!=0',attr: ['5', 'base'], type: 4},
   {bits: 5,  name: 'cs2',       attr: ['5', 'src'], type: 4},
   {bits: 7,  name: 'imm[11:5]', attr: ['7', 'offset[11:5]'], type: 3},
 ]}
Original file line number	Diff line number	Diff line change
		@@ -0,0 +1,2 @@
		NOTE: Any instance of this instruction with a `cs1` of `c0` would certainly trap (with a CHERI tag violation), as `c0` is defined to always hold a <<null-cap>> capability.
		As such, the encodings with a `cs1` of `c0` are RESERVED for use by future extensions.