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Merge pull request #33 from tariqkurd-repo/shift_and_add
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correct shift and add operands
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tariqkurd-repo authored Jan 24, 2024
2 parents 1c969c6 + afa986f commit 991ee95
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Showing 4 changed files with 12 additions and 12 deletions.
6 changes: 3 additions & 3 deletions src/insns/sh123add_32bit.adoc
Original file line number Diff line number Diff line change
Expand Up @@ -43,16 +43,16 @@ Encoding::
{ bits: 5, name: 'rd' },
{ bits: 3, name: 0x2, attr: ['SH1ADD=010', 'CSH1ADD=010', 'SH2ADD=100', 'CSH2ADD=100', 'SH3ADD=110', 'CSH3ADD=110'] },
{ bits: 5, name: 'rs1' },
{ bits: 5, name: 'rs2' },
{ bits: 5, name: 'cs2/rs2' },
{ bits: 7, name: 0x10, attr: ['SH[1|2|3]ADD', 'CSH[1|2|3]ADD'] },
]}
....

Capability Mode Description::
Increment the address field of `cs1` by `rs2` shifted left by _n_ bit positions. Clear the tag if the resulting capability is unrepresentable or `cs1` is sealed.
Increment the address field of `cs2` by `rs1` shifted left by _n_ bit positions. Clear the tag if the resulting capability is unrepresentable or `cs2` is sealed.

Legacy Mode Description::
Increment the address field of `rs1` by `rs2` shifted left by _n_ bit positions.
Increment `rs2` by `rs1` shifted left by _n_ bit positions.

Prerequisites CSH[1|2|3]ADD::
{cheri_base_ext_name}, Zba
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6 changes: 3 additions & 3 deletions src/insns/sh123adduw_32bit.adoc
Original file line number Diff line number Diff line change
Expand Up @@ -43,16 +43,16 @@ Encoding::
{ bits: 5, name: 'rd' },
{ bits: 3, name: 0x2, attr: ['rv64: SH1ADD.UW=010', 'rv64: CSH1ADD.UW=010', 'rv64: SH2ADD.UW=100', 'rv64: CSH2ADD.UW=100', 'rv64: SH3ADD.UW=110', 'rv64: CSH3ADD.UW=110'] },
{ bits: 5, name: 'rs1' },
{ bits: 5, name: 'rs2' },
{ bits: 5, name: 'cs2/rs2' },
{ bits: 7, name: 0x10, attr: ['rv64: SH[1|2|3]ADD.UW', 'rv64: CSH[1|2|3]ADD.UW'] },
]}
....

Capability Mode Description::
Increment the address field of `cs1` by the unsigned word in `rs2` shifted left by _n_ bit positions. Clear the tag if the resulting capability is unrepresentable or `cs1` is sealed.
Increment the address field of `cs2` by the unsigned word in `rs1` shifted left by _n_ bit positions. Clear the tag if the resulting capability is unrepresentable or `cs2` is sealed.

Legacy Mode Description::
Increment the address field of `rs1` by the unsigned word in `rs2` shifted left by _n_ bit positions.
Increment `rs2` by the unsigned word in `rs1` shifted left by _n_ bit positions.

Prerequisites CSH[1|2|3]ADD.UW::
{cheri_base_ext_name}, Zba
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6 changes: 3 additions & 3 deletions src/insns/sh4add_32bit.adoc
Original file line number Diff line number Diff line change
Expand Up @@ -30,16 +30,16 @@ Encoding::
{ bits: 5, name: 'rd' },
{ bits: 3, name: 0x7, attr: ['CSH4ADD','SH4ADD'] },
{ bits: 5, name: 'rs1' },
{ bits: 5, name: 'rs2' },
{ bits: 5, name: 'cs2/rs2' },
{ bits: 7, name: 16, attr: ['CSH4ADD','SH4ADD'] },
]}
....

Capability Mode Description::
Increment the address field of `cs1` by `rs2` shifted left by 4 bit positions. Clear the tag if the resulting capability is unrepresentable or `cs1` is sealed.
Increment the address field of `cs2` by `rs1` shifted left by 4 bit positions. Clear the tag if the resulting capability is unrepresentable or `cs2` is sealed.

Legacy Mode Description::
Increment the address field of `rs1` by `rs2` shifted left by 4 bit positions.
Increment `rs2` by `rs1` shifted left by 4 bit positions.

Prerequisites CSH4ADD::
{cheri_base_ext_name}
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6 changes: 3 additions & 3 deletions src/insns/sh4adduw_32bit.adoc
Original file line number Diff line number Diff line change
Expand Up @@ -26,16 +26,16 @@ Encoding::
{ bits: 5, name: 'rd' },
{ bits: 3, name: 0x7, attr: ['CSH4ADD.UW', 'SH4ADD.UW'] },
{ bits: 5, name: 'rs1' },
{ bits: 5, name: 'rs2' },
{ bits: 5, name: 'cs2/rs2' },
{ bits: 7, name: 16, attr: ['CSH4ADD.UW', 'SH4ADD.UW'] },
]}
....

Capability Mode Description::
Increment the address field of `cs1` by the unsigned word in `rs2` shifted left by 4 bit positions. Clear the tag if the resulting capability is unrepresentable or `cs1` is sealed.
Increment the address field of `cs2` by the unsigned word in `rs1` shifted left by 4 bit positions. Clear the tag if the resulting capability is unrepresentable or `cs2` is sealed.

Legacy Mode Description::
Increment the address field of `rs1` by the unsigned word in `rs2` shifted left by 4 bit positions.
Increment `rs2` by the unsigned word in `rs1` shifted left by 4 bit positions.

Prerequisites CSH4ADD::
{cheri_base_ext_name}
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