Merge branch 'master' into pr-stimecmp

riscv-software-src · Nov 23, 2023 · 22a3b11 · 22a3b11
2 parents 6367b06 + 4841ad0
commit 22a3b11
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diff --git a/.github/workflows/continuous-integration.yml b/.github/workflows/continuous-integration.yml
@@ -21,23 +21,37 @@ jobs:
     runs-on: ubuntu-20.04
     steps:
       - uses: actions/checkout@v2
+        with:
+          # checkout full tree
+          fetch-depth: 0
 
       - name: Install Dependencies
         run: sudo xargs apt-get install -y < .github/workflows/apt-packages.txt
 
       - run: |
-          ci-tests/build-spike
-          ci-tests/test-spike
+          for commit in $(git rev-list origin/master..HEAD); do
+            git checkout $commit
+            echo "Checking commit $commit"
+            ci-tests/build-spike
+            ci-tests/test-spike
+          done
 
   test-macos:
     name: Test Spike build (MacOS)
     runs-on: macos-12
     steps:
       - uses: actions/checkout@v2
+        with:
+          # checkout full tree
+          fetch-depth: 0
 
       - name: Install Dependencies
-        run: xargs brew install < .github/workflows/brew-packages.txt
+        run: xargs brew install --overwrite < .github/workflows/brew-packages.txt
 
       - run: |
-          ci-tests/build-spike
-          ci-tests/test-spike
+          for commit in $(git rev-list origin/master..HEAD); do
+            git checkout $commit
+            echo "Checking commit $commit"
+            ci-tests/build-spike
+            ci-tests/test-spike
+          done
diff --git a/.github/workflows/debug-smoke.yml b/.github/workflows/debug-smoke.yml
@@ -25,7 +25,7 @@ jobs:
         run: |
           git clone --recurse-submodules https://github.com/riscv/riscv-openocd.git
           cd riscv-openocd
-          git checkout 43ea20dfbb6c815004a51106a3b2009d7f6c4940
+          git checkout a495dd854ce2e857a583125a31527a47320ec6b9
 
       - name: Build OpenOCD
         run: |
@@ -47,7 +47,7 @@ jobs:
         run: |
           git clone --recurse-submodules https://github.com/riscv-software-src/riscv-tests.git
           cd riscv-tests
-          git checkout c84daca8824635b7d896003c78f9c6245997cf7a
+          git checkout bd0a19c136927eaa3b7296a591a896c141affb6b
 
       - name: Run Tests
         run: |

diff --git a/Makefile.in b/Makefile.in
@@ -98,7 +98,7 @@ default-CXXFLAGS := $(default-CFLAGS) -std=c++17
 
 mcppbs-CPPFLAGS := @CPPFLAGS@
 mcppbs-CFLAGS   := $(default-CFLAGS) @CFLAGS@
-mcppbs-CXXFLAGS := $(mcppbs-CFLAGS) $(default-CXXFLAGS) @CXXFLAGS@
+mcppbs-CXXFLAGS := $(default-CXXFLAGS) @CXXFLAGS@
 
 CC            := @CC@
 CXX           := @CXX@
@@ -256,15 +256,15 @@ $(2)_test_objs      := $$(patsubst %.cc, %.o, $$($(2)_test_srcs))
 $(2)_test_deps      := $$(patsubst %.o, %.d, $$($(2)_test_objs))
 $(2)_test_exes      := $$(patsubst %.t.cc, %-utst, $$($(2)_test_srcs))
 $(2)_test_outs      := $$(patsubst %, %.out, $$($(2)_test_exes))
-$(2)_test_libs      := $(1) $$($(2)_reverse_deps) utst
+$(2)_test_libs      := $(1) $$($(2)_reverse_deps)
 $(2)_test_libnames  := $$(patsubst %, lib%.a, $$($(2)_test_libs))
 $(2)_test_libarg    := $$(patsubst %, -l%, $$($(2)_test_libs))
 
 $$($(2)_test_objs) : %.o : %.cc
 	$(COMPILE) -c $$<
 
 $$($(2)_test_exes) : %-utst : %.t.o $$($(2)_test_libnames)
-	$(LINK) -o $$@ $$< $$($(2)_test_libnames) $(LIBS)
+	$(LINK) $$($(2)_LDFLAGS) -o $$@ $$< $$($(2)_test_libnames) $(LIBS)
 
 $(2)_deps += $$($(2)_test_deps)
 $(2)_junk += \
@@ -274,7 +274,8 @@ $(2)_junk += \
 # Run unit tests
 
 $$($(2)_test_outs) : %.out : %
-	$(RUN) $(RUNFLAGS) ./$$< default | tee $$@
+	./$$< default
+	touch $$@
 
 $(2)_junk += $$($(2)_test_outs)
 
@@ -291,7 +292,7 @@ $$($(2)_prog_objs) : %.o : %.cc
 	$(COMPILE) -c $$<
 
 $$($(2)_prog_exes) : % : %.o $$($(2)_prog_libnames)
-	$(LINK) -o $$@ $$< $$($(2)_prog_libnames) $(LIBS)
+	$(LINK) $$($(2)_LDFLAGS) -o $$@ $$< $$($(2)_prog_libnames) $(LIBS)
 
 $(2)_deps += $$($(2)_prog_deps)
 $(2)_junk += $$($(2)_prog_objs) $$($(2)_prog_deps) $$($(2)_prog_exes)
@@ -306,7 +307,7 @@ $$($(2)_install_prog_objs) : %.o : %.cc $$($(2)_gen_hdrs)
 	$(COMPILE) -c $$<
 
 $$($(2)_install_prog_exes) : % : %.o $$($(2)_prog_libnames)
-	$(LINK) -o $$@ $$< $$($(2)_prog_libnames) $(LIBS)
+	$(LINK) $$($(2)_LDFLAGS) -o $$@ $$< $$($(2)_prog_libnames) $(LIBS)
 
 $(2)_deps += $$($(2)_install_prog_deps)
 $(2)_junk += \
@@ -318,7 +319,7 @@ $(2)_junk += \
 all-$(1) : lib$(1).a $$($(2)_install_prog_exes)
 
 check-$(1) : $$($(2)_test_outs)
-	echo; grep -h -e'Unit Tests' -e'FAILED' -e'Segementation' $$^; echo
+	echo; grep -h -e'Unit Tests' -e'FAILED' -e'Segmentation' $$^; echo
 
 clean-$(1) :
 	rm -rf $$($(2)_junk)
@@ -359,20 +360,8 @@ deps : $(deps)
 # Check
 #-------------------------------------------------------------------------
 
-bintest_outs = $(bintests:=.out)
-junk += $(bintest_outs)
-%.out: % all
-	./$* < /dev/null 2>&1 | tee $@
-
-check-cpp : $(test_outs)
-	@echo
-	! grep -h -e'Unit Tests' -e'FAILED' -e'Segmentation' $^ < /dev/null
-	@echo
-
-check-bin : $(bintest_outs)
-	! tail -n 1 $^ < /dev/null 2>&1 | grep FAILED
-
-check : check-cpp check-bin
+check : $(test_outs)
+	echo; grep -h -e'Unit Tests' -e'FAILED' -e'Segementation' $^ < /dev/null; echo
 
 .PHONY : check
 

diff --git a/README.md b/README.md
@@ -49,20 +49,9 @@ Spike supports the following RISC-V ISA features:
   - Zcd extension, v1.0
   - Zcmp extension, v1.0
   - Zcmt extension, v1.0
-
-As a Spike extension, the remainder of the proposed
-[Bit-Manipulation Extensions](https://github.com/riscv/riscv-bitmanip)
-is provided under the Spike-custom extension name _Xbitmanip_.
-These instructions (and, of course, the extension name) are not RISC-V
-standards.
-
-These proposed bit-manipulation extensions can be split into further
-groups: Zbp, Zbs, Zbe, Zbf, Zbc, Zbm, Zbr, Zbt. Note that Zbc is
-ratified, but the original proposal contained some extra instructions
-(64-bit carryless multiplies) which are captured here.
-
-To enable these extensions individually, use the Spike-custom
-extension names _XZbp_, _XZbs_, _XZbc_, and so on.
+  - Zfbfmin extension, v0.6
+  - Zvfbfmin extension, v0.6
+  - Zvfbfwma extension, v0.6
 
 Versioning and APIs
 -------------------
@@ -141,7 +130,10 @@ Adding an instruction to the simulator requires two steps:
          $ make install
         ```
 
-  3.  Rebuild the simulator.
+  3.  Add the instruction to riscv/riscv.mk.in. Otherwise, the instruction
+      will not be included in the build and will be treated as an illegal instruction.
+
+  4.  Rebuild the simulator.
 
 Interactive Debug Mode
 ---------------------------

diff --git a/arch_test_target/spike/model_test.h b/arch_test_target/spike/model_test.h
@@ -49,16 +49,50 @@
 //RVTEST_IO_ASSERT_DFPR_EQ
 #define RVMODEL_IO_ASSERT_DFPR_EQ(_D, _R, _I)
 
-#define RVMODEL_SET_MSW_INT       \
- li t1, 1;                         \
- li t2, 0x2000000;                 \
- sw t1, 0(t2);
+#ifndef RVMODEL_MCLINTBASE    
+        #define RVMODEL_MCLINTBASE 0x02000000
+#endif
+
+#ifndef RVMODEL_MSIP_OFFSET    
+        #define RVMODEL_MSIP_OFFSET 0x0
+#endif
+
+#ifndef RVMODEL_MTIMECMP_OFFSET    
+        #define RVMODEL_MTIMECMP_OFFSET 0x4000
+#endif
+
+#ifndef RVMODEL_MTIMECMPH_OFFSET    
+        #define RVMODEL_MTIMECMPH_OFFSET 0x4004
+#endif
+
+#define RVMODEL_SET_MSW_INT                                                           \
+    lui t0,      ((RVMODEL_MCLINTBASE + RVMODEL_MSIP_OFFSET)>> 12);         \
+    addi t0, t0, ((RVMODEL_MCLINTBASE + RVMODEL_MSIP_OFFSET) & 0xFFF);      \
+    li t1, 1;                                                                         \
+    sw t1, (t0);                                                                      \
+
+#define RVMODEL_CLEAR_MSW_INT                                                         \
+    lui t0,      ((RVMODEL_MCLINTBASE + RVMODEL_MSIP_OFFSET)>> 12);         \
+    addi t0, t0, ((RVMODEL_MCLINTBASE + RVMODEL_MSIP_OFFSET) & 0xFFF);      \
+    sw x0, (t0);                                                                      \
 
-#define RVMODEL_CLEAR_MSW_INT     \
- li t2, 0x2000000;                 \
- sw x0, 0(t2);
+#define RVMODEL_SET_MTIMER_INT                                                        \
+    lui t0,      ((RVMODEL_MCLINTBASE + RVMODEL_MTIMECMP_OFFSET)>> 12);     \
+    addi t0, t0, ((RVMODEL_MCLINTBASE + RVMODEL_MTIMECMP_OFFSET) & 0xFFF);  \
+    sw x0, (t0);                                                                      \
+    lui t0,      ((RVMODEL_MCLINTBASE + RVMODEL_MTIMECMPH_OFFSET)>> 12);    \
+    addi t0, t0, ((RVMODEL_MCLINTBASE + RVMODEL_MTIMECMPH_OFFSET) & 0xFFF); \
+    sw x0, (t0);                                                                      \
 
-#define RVMODEL_CLEAR_MTIMER_INT
+#define RVMODEL_CLEAR_MTIMER_INT                                                      \
+    addi t1,x0,1;                                                          \
+    neg t1,t1;                                                                         \
+    lui t0,      ((RVMODEL_MCLINTBASE + RVMODEL_MTIMECMPH_OFFSET)>> 12);    \
+    addi t0, t0, ((RVMODEL_MCLINTBASE + RVMODEL_MTIMECMPH_OFFSET) & 0xFFF); \
+    sw t1, (t0);                                                                      \
+    lui t0,      ((RVMODEL_MCLINTBASE + RVMODEL_MTIMECMP_OFFSET)>> 12);     \
+    addi t0, t0, ((RVMODEL_MCLINTBASE + RVMODEL_MTIMECMP_OFFSET) & 0xFFF);  \
+    sw t1, (t0);                                                                      \
 
 #define RVMODEL_CLEAR_MEXT_INT
 

diff --git a/ci-tests/build-spike b/ci-tests/build-spike
@@ -3,11 +3,14 @@ set -e
 
 DIR="$( cd "$( dirname "${BASH_SOURCE[0]}" )" >/dev/null 2>&1 && pwd )"
 
+rm -rf build
+
 mkdir build
 cd build
 mkdir install
 CXXFLAGS="-Wnon-virtual-dtor" CFLAGS="-Werror -Wignored-qualifiers -Wunused-function -Wunused-parameter -Wunused-variable" $DIR/../configure --prefix=`pwd`/install
 make -j"$(nproc 2> /dev/null || sysctl -n hw.ncpu)"
+make check
 make install
 
 # check that help message prints without error

diff --git a/ci-tests/testlib.c b/ci-tests/testlib.c
@@ -2,9 +2,9 @@
 
 // Copied from spike main.
 // TODO: This should really be provided in libriscv
-static std::vector<std::pair<reg_t, mem_t*>> make_mems(const std::vector<mem_cfg_t> &layout)
+static std::vector<std::pair<reg_t, abstract_mem_t*>> make_mems(const std::vector<mem_cfg_t> &layout)
 {
-  std::vector<std::pair<reg_t, mem_t*>> mems;
+  std::vector<std::pair<reg_t, abstract_mem_t*>> mems;
   mems.reserve(layout.size());
   for (const auto &cfg : layout) {
     mems.push_back(std::make_pair(cfg.get_base(), new mem_t(cfg.get_size())));
@@ -24,11 +24,12 @@ int main()
             false,
             endianness_little,
             16,
+            (1 << PMP_SHIFT),
             mem_cfg,
             hartids,
             false,
             4);
-  std::vector<std::pair<reg_t, abstract_device_t*>> plugin_devices;
+  std::vector<const device_factory_t*> plugin_devices;
   std::vector<std::string> htif_args {"pk", "hello"};
   debug_module_config_t dm_config = {
     .progbufsize = 2,
@@ -41,7 +42,8 @@ int main()
     .support_haltgroups = true,
     .support_impebreak = true
   };
-  std::vector<std::pair<reg_t, mem_t*>> mems = make_mems(cfg.mem_layout());
+  std::vector<std::pair<reg_t, abstract_mem_t*>> mems =
+      make_mems(cfg.mem_layout());
   sim_t sim(&cfg, false,
             mems,
             plugin_devices,