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Merge pull request #51 from pulp-platform/verilator_clang
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Verilation with LLVM
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suehtamacv authored Jul 12, 2021
2 parents 86a4376 + 89f4d4e commit 76305f1
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Showing 4 changed files with 17 additions and 3 deletions.
13 changes: 11 additions & 2 deletions .github/workflows/ci.yml
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Expand Up @@ -138,13 +138,18 @@ jobs:
cache-name: cache-verilator
with:
path: install/verilator
key: ${{ runner.os }}-build-${{ env.cache-name }}-${{ env.tc-verilator-hash }}
key: ${{ runner.os }}-build-llvm10-${{ env.cache-name }}-${{ env.tc-verilator-hash }}
restore-keys:
${{ runner.os }}-build-${{ env.cache-name }}-${{ env.tc-verilator-hash }}
${{ runner.os }}-build-llvm10-${{ env.cache-name }}-${{ env.tc-verilator-hash }}
- name: Download Verilator
if: steps.tc-verilator-cache.outputs.cache-hit != 'true'
run: |
git submodule update --init --recursive -- toolchain/verilator
- name: Install LLVM and Clang
if: steps.tc-verilator-cache.outputs.cache-hit != 'true'
uses: KyleMayes/install-llvm-action@v1
with:
version: "10.0"
- name: Compile Verilator
if: steps.tc-verilator-cache.outputs.cache-hit != 'true'
run: |
Expand Down Expand Up @@ -249,6 +254,10 @@ jobs:
ln -s $VERILATOR_ROOT/share/verilator/bin/verilator_includer $VERILATOR_ROOT/bin/verilator_includer
- name: Download RTL submodules
run: git submodule update --init --recursive hardware
- name: Install LLVM and Clang
uses: KyleMayes/install-llvm-action@v1
with:
version: "10.0"
- name: Compile Verilated model of Ara
run: |
sudo apt-get install libelf-dev
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4 changes: 4 additions & 0 deletions CHANGELOG.md
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Expand Up @@ -10,6 +10,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.

- Format source files in the `apps` folder with clang-format by running `make format`

### Changed

- Compile Verilator and Ara's verilated model with LLVM, for a faster compile time.

## 2.0.0 - 2021-06-24

### Added
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2 changes: 1 addition & 1 deletion Makefile
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Expand Up @@ -131,7 +131,7 @@ ${VERIL_INSTALL_DIR}: Makefile
cd $(CURDIR)/toolchain/verilator && git reset --hard && git fetch && git checkout ${VERIL_VERSION}
# Compile verilator
cd $(CURDIR)/toolchain/verilator && git clean -xfdf && autoconf && \
./configure --prefix=$(VERIL_INSTALL_DIR) && make -j4 && make install
CC=clang CXX=clang++ ./configure --prefix=$(VERIL_INSTALL_DIR) && make -j4 && make install

# RISC-V Tests
riscv_tests:
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1 change: 1 addition & 0 deletions hardware/Makefile
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Expand Up @@ -142,6 +142,7 @@ $(veril_library)/V$(veril_top): Makefile ../Bender.yml $(shell find src -type f)
-Wno-WIDTHCONCAT \
--Mdir $(veril_library) --trace \
-Itb/dpi \
--compiler clang \
-CFLAGS "-std=c++11 -Wall -DTOPLEVEL_NAME=$(veril_top)" \
-CFLAGS "-DNR_LANES=$(nr_lanes)" \
-CFLAGS -I$(ROOT_DIR)/tb/verilator/lowrisc_dv_verilator_memutil_dpi/cpp \
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