Fix

openvm-org · Jan 21, 2025 · b772fb0 · b772fb0
1 parent 4b7f57e
commit b772fb0
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Showing 5 changed files with 37 additions and 13 deletions.
diff --git a/extensions/bigint/circuit/src/tests.rs b/extensions/bigint/circuit/src/tests.rs
@@ -199,7 +199,7 @@ fn run_mul_256_rand_test(num_ops: usize) {
     );
 
     run_int_256_rand_execute(
-        MulOpcode::MUL as usize,
+        MulOpcode::MUL.global_opcode().as_usize(),
         num_ops,
         &mut chip,
         &mut tester,
@@ -285,7 +285,7 @@ fn run_beq_256_rand_test(opcode: BranchEqualOpcode, num_ops: usize) {
         x.iter()
             .zip(y.iter())
             .fold(true, |acc, (x, y)| acc && (x == y))
-            ^ (opcode == BranchEqualOpcode::BNE as usize)
+            ^ (opcode == BranchEqualOpcode::BNE.global_opcode().as_usize())
     };
 
     run_int_256_rand_execute(
@@ -327,7 +327,7 @@ fn run_blt_256_rand_test(opcode: BranchLessThanOpcode, num_ops: usize) {
     );
 
     let branch_fn = |opcode: usize, x: &[u32; INT256_NUM_LIMBS], y: &[u32; INT256_NUM_LIMBS]| {
-        let opcode = BranchLessThanOpcode::from_usize(opcode);
+        let opcode = BranchLessThanOpcode::from_usize(opcode - BranchLessThanOpcode::CLASS_OFFSET);
         let (is_ge, is_signed) = match opcode {
             BranchLessThanOpcode::BLT => (false, true),
             BranchLessThanOpcode::BLTU => (false, false),

diff --git a/extensions/native/circuit/src/field_extension/core.rs b/extensions/native/circuit/src/field_extension/core.rs
@@ -93,7 +93,7 @@ where
             builder.assert_bool(flag);
 
             is_valid += flag.into();
-            expected_opcode += flag * AB::F::from_canonical_usize(opcode as usize);
+            expected_opcode += flag * AB::F::from_canonical_usize(opcode.local_usize());
 
             for (j, result_part) in result.into_iter().enumerate() {
                 expected_result[j] += flag * result_part;

diff --git a/extensions/native/circuit/src/poseidon2/tests.rs b/extensions/native/circuit/src/poseidon2/tests.rs
@@ -89,7 +89,7 @@ fn tester_with_random_poseidon2_ops(
             tester.write_cell(d, c, BabyBear::from_canonical_usize(rhs));
         }
 
-        let local_opcode = Poseidon2Opcode::from_usize(opcode - Poseidon2Opcode::CLASS_OFFSET);
+        let local_opcode = Poseidon2Opcode::from_usize(opcode);
 
         match local_opcode {
             Poseidon2Opcode::COMP_POS2 => {

diff --git a/extensions/rv32im/circuit/src/less_than/tests.rs b/extensions/rv32im/circuit/src/less_than/tests.rs
@@ -70,8 +70,14 @@ fn run_rv32_lt_rand_test(opcode: LessThanOpcode, num_ops: usize) {
             (Some(imm), c)
         };
 
-        let (instruction, rd) =
-            rv32_rand_write_register_or_imm(&mut tester, b, c, c_imm, opcode as usize, &mut rng);
+        let (instruction, rd) = rv32_rand_write_register_or_imm(
+            &mut tester,
+            b,
+            c,
+            c_imm,
+            opcode.global_opcode().as_usize(),
+            &mut rng,
+        );
         tester.execute(&mut chip, &instruction);
 
         let (cmp, _, _, _) =
@@ -83,13 +89,25 @@ fn run_rv32_lt_rand_test(opcode: LessThanOpcode, num_ops: usize) {
 
     // Test special case where b = c
     let b = [101, 128, 202, 255];
-    let (instruction, _) =
-        rv32_rand_write_register_or_imm(&mut tester, b, b, None, opcode as usize, &mut rng);
+    let (instruction, _) = rv32_rand_write_register_or_imm(
+        &mut tester,
+        b,
+        b,
+        None,
+        opcode.global_opcode().as_usize(),
+        &mut rng,
+    );
     tester.execute(&mut chip, &instruction);
 
     let b = [36, 0, 0, 0];
-    let (instruction, _) =
-        rv32_rand_write_register_or_imm(&mut tester, b, b, Some(36), opcode as usize, &mut rng);
+    let (instruction, _) = rv32_rand_write_register_or_imm(
+        &mut tester,
+        b,
+        b,
+        Some(36),
+        opcode.global_opcode().as_usize(),
+        &mut rng,
+    );
     tester.execute(&mut chip, &instruction);
 
     let tester = tester.build().load(chip).load(bitwise_chip).finalize();

diff --git a/extensions/rv32im/circuit/src/shift/tests.rs b/extensions/rv32im/circuit/src/shift/tests.rs
@@ -73,8 +73,14 @@ fn run_rv32_shift_rand_test(opcode: ShiftOpcode, num_ops: usize) {
             (Some(imm), c)
         };
 
-        let (instruction, rd) =
-            rv32_rand_write_register_or_imm(&mut tester, b, c, c_imm, opcode as usize, &mut rng);
+        let (instruction, rd) = rv32_rand_write_register_or_imm(
+            &mut tester,
+            b,
+            c,
+            c_imm,
+            opcode.global_opcode().as_usize(),
+            &mut rng,
+        );
         tester.execute(&mut chip, &instruction);
 
         let (a, _, _) = run_shift::<RV32_REGISTER_NUM_LIMBS, RV32_CELL_BITS>(opcode, &b, &c);