Fix

extensions/bigint/circuit/src/extension.rs

@@ -141,7 +141,7 @@ impl<F: PrimeField32> VmExtension<F> for Int256 {
                 address_bits,
                 bitwise_lu_chip.clone(),
             ),
-            BaseAluCoreChip::new(bitwise_lu_chip.clone()),
+            BaseAluCoreChip::new(bitwise_lu_chip.clone(), Rv32BaseAlu256Opcode::CLASS_OFFSET),
             offline_memory.clone(),
         );
         inventory.add_executor(
@@ -208,7 +208,7 @@ impl<F: PrimeField32> VmExtension<F> for Int256 {
                 address_bits,
                 bitwise_lu_chip.clone(),
             ),
-            MultiplicationCoreChip::new(range_tuple_chip),
+            MultiplicationCoreChip::new(range_tuple_chip, Rv32Mul256Opcode::CLASS_OFFSET),
             offline_memory.clone(),
         );
         inventory.add_executor(
@@ -224,7 +224,11 @@ impl<F: PrimeField32> VmExtension<F> for Int256 {
                 address_bits,
                 bitwise_lu_chip.clone(),
             ),
-            ShiftCoreChip::new(bitwise_lu_chip.clone(), range_checker_chip),
+            ShiftCoreChip::new(
+                bitwise_lu_chip.clone(),
+                range_checker_chip,
+                Rv32Shift256Opcode::CLASS_OFFSET,
+            ),
             offline_memory.clone(),
         );
         inventory.add_executor(

extensions/bigint/circuit/src/tests.rs

@@ -1,3 +1,4 @@
+use openvm_bigint_transpiler::{Rv32BaseAlu256Opcode, Rv32Mul256Opcode, Rv32Shift256Opcode};
 use openvm_circuit::{
     arch::{
         testing::VmChipTestBuilder, InstructionExecutor, BITWISE_OP_LOOKUP_BUS,
@@ -20,7 +21,7 @@ use openvm_rv32im_circuit::{
     MultiplicationCoreChip, ShiftCoreChip,
 };
 use openvm_rv32im_transpiler::{
-    BaseAluOpcode, BranchEqualOpcode, BranchLessThanOpcode, LessThanOpcode, MulOpcode, ShiftOpcode,
+    BaseAluOpcode, BranchEqualOpcode, BranchLessThanOpcode, LessThanOpcode, ShiftOpcode,
 };
 use openvm_stark_backend::p3_field::{FieldAlgebra, PrimeField32};
 use openvm_stark_sdk::{p3_baby_bear::BabyBear, utils::create_seeded_rng};
@@ -95,7 +96,7 @@ fn run_alu_256_rand_test(opcode: BaseAluOpcode, num_ops: usize) {
             tester.address_bits(),
             bitwise_chip.clone(),
         ),
-        BaseAluCoreChip::new(bitwise_chip.clone()),
+        BaseAluCoreChip::new(bitwise_chip.clone(), Rv32BaseAlu256Opcode::CLASS_OFFSET),
         tester.offline_memory_mutex_arc(),
     );
 
@@ -194,12 +195,12 @@ fn run_mul_256_rand_test(num_ops: usize) {
             tester.address_bits(),
             bitwise_chip.clone(),
         ),
-        MultiplicationCoreChip::new(range_tuple_checker.clone()),
+        MultiplicationCoreChip::new(range_tuple_checker.clone(), Rv32Mul256Opcode::CLASS_OFFSET),
         tester.offline_memory_mutex_arc(),
     );
 
     run_int_256_rand_execute(
-        MulOpcode::MUL.global_opcode().as_usize(),
+        Rv32Mul256Opcode::CLASS_OFFSET,
         num_ops,
         &mut chip,
         &mut tester,
@@ -235,6 +236,7 @@ fn run_shift_256_rand_test(opcode: ShiftOpcode, num_ops: usize) {
         ShiftCoreChip::new(
             bitwise_chip.clone(),
             tester.memory_controller().borrow().range_checker.clone(),
+            Rv32Shift256Opcode::CLASS_OFFSET,
         ),
         tester.offline_memory_mutex_arc(),
     );

extensions/rv32im/circuit/src/base_alu/core.rs

@@ -41,6 +41,7 @@ pub struct BaseAluCoreCols<T, const NUM_LIMBS: usize, const LIMB_BITS: usize> {
 #[derive(Copy, Clone, Debug)]
 pub struct BaseAluCoreAir<const NUM_LIMBS: usize, const LIMB_BITS: usize> {
     pub bus: BitwiseOperationLookupBus,
+    offset: usize,
 }
 
 impl<F: Field, const NUM_LIMBS: usize, const LIMB_BITS: usize> BaseAir<F>
@@ -160,7 +161,7 @@ where
     }
 
     fn start_offset(&self) -> usize {
-        BaseAluOpcode::CLASS_OFFSET
+        self.offset
     }
 }
 
@@ -182,10 +183,14 @@ pub struct BaseAluCoreChip<const NUM_LIMBS: usize, const LIMB_BITS: usize> {
 }
 
 impl<const NUM_LIMBS: usize, const LIMB_BITS: usize> BaseAluCoreChip<NUM_LIMBS, LIMB_BITS> {
-    pub fn new(bitwise_lookup_chip: SharedBitwiseOperationLookupChip<LIMB_BITS>) -> Self {
+    pub fn new(
+        bitwise_lookup_chip: SharedBitwiseOperationLookupChip<LIMB_BITS>,
+        offset: usize,
+    ) -> Self {
         Self {
             air: BaseAluCoreAir {
                 bus: bitwise_lookup_chip.bus(),
+                offset,
             },
             bitwise_lookup_chip,
         }
@@ -211,8 +216,7 @@ where
         reads: I::Reads,
     ) -> Result<(AdapterRuntimeContext<F, I>, Self::Record)> {
         let Instruction { opcode, .. } = instruction;
-        let local_opcode =
-            BaseAluOpcode::from_usize(opcode.local_opcode_idx(BaseAluOpcode::CLASS_OFFSET));
+        let local_opcode = BaseAluOpcode::from_usize(opcode.local_opcode_idx(self.air.offset));
 
         let data: [[F; NUM_LIMBS]; 2] = reads.into();
         let b = data[0].map(|x| x.as_canonical_u32());
@@ -245,10 +249,7 @@ where
     }
 
     fn get_opcode_name(&self, opcode: usize) -> String {
-        format!(
-            "{:?}",
-            BaseAluOpcode::from_usize(opcode - BaseAluOpcode::CLASS_OFFSET)
-        )
+        format!("{:?}", BaseAluOpcode::from_usize(opcode - self.air.offset))
     }
 
     fn generate_trace_row(&self, row_slice: &mut [F], record: Self::Record) {

extensions/rv32im/circuit/src/base_alu/tests.rs

@@ -54,7 +54,7 @@ fn run_rv32_alu_rand_test(opcode: BaseAluOpcode, num_ops: usize) {
             tester.program_bus(),
             tester.memory_bridge(),
         ),
-        BaseAluCoreChip::new(bitwise_chip.clone()),
+        BaseAluCoreChip::new(bitwise_chip.clone(), BaseAluOpcode::CLASS_OFFSET),
         tester.offline_memory_mutex_arc(),
     );
 
@@ -143,7 +143,7 @@ fn run_rv32_alu_negative_test(
             vec![None],
             ExecutionBridge::new(tester.execution_bus(), tester.program_bus()),
         ),
-        BaseAluCoreChip::new(bitwise_chip.clone()),
+        BaseAluCoreChip::new(bitwise_chip.clone(), BaseAluOpcode::CLASS_OFFSET),
         tester.offline_memory_mutex_arc(),
     );
 

extensions/rv32im/circuit/src/extension.rs

@@ -237,7 +237,7 @@ impl<F: PrimeField32> VmExtension<F> for Rv32I {
 
         let base_alu_chip = Rv32BaseAluChip::new(
             Rv32BaseAluAdapterChip::new(execution_bus, program_bus, memory_bridge),
-            BaseAluCoreChip::new(bitwise_lu_chip.clone()),
+            BaseAluCoreChip::new(bitwise_lu_chip.clone(), BaseAluOpcode::CLASS_OFFSET),
             offline_memory.clone(),
         );
         inventory.add_executor(
@@ -254,7 +254,11 @@ impl<F: PrimeField32> VmExtension<F> for Rv32I {
 
         let shift_chip = Rv32ShiftChip::new(
             Rv32BaseAluAdapterChip::new(execution_bus, program_bus, memory_bridge),
-            ShiftCoreChip::new(bitwise_lu_chip.clone(), range_checker.clone()),
+            ShiftCoreChip::new(
+                bitwise_lu_chip.clone(),
+                range_checker.clone(),
+                ShiftOpcode::CLASS_OFFSET,
+            ),
             offline_memory.clone(),
         );
         inventory.add_executor(shift_chip, ShiftOpcode::iter().map(|x| x.global_opcode()))?;
@@ -403,7 +407,7 @@ impl<F: PrimeField32> VmExtension<F> for Rv32M {
 
         let mul_chip = Rv32MultiplicationChip::new(
             Rv32MultAdapterChip::new(execution_bus, program_bus, memory_bridge),
-            MultiplicationCoreChip::new(range_tuple_checker.clone()),
+            MultiplicationCoreChip::new(range_tuple_checker.clone(), MulOpcode::CLASS_OFFSET),
             offline_memory.clone(),
         );
         inventory.add_executor(mul_chip, MulOpcode::iter().map(|x| x.global_opcode()))?;

extensions/rv32im/circuit/src/mul/core.rs

@@ -32,6 +32,7 @@ pub struct MultiplicationCoreCols<T, const NUM_LIMBS: usize, const LIMB_BITS: us
 #[derive(Copy, Clone, Debug)]
 pub struct MultiplicationCoreAir<const NUM_LIMBS: usize, const LIMB_BITS: usize> {
     pub bus: RangeTupleCheckerBus<2>,
+    pub offset: usize,
 }
 
 impl<F: Field, const NUM_LIMBS: usize, const LIMB_BITS: usize> BaseAir<F>
@@ -102,7 +103,7 @@ where
     }
 
     fn start_offset(&self) -> usize {
-        MulOpcode::CLASS_OFFSET
+        self.offset
     }
 }
 
@@ -113,7 +114,7 @@ pub struct MultiplicationCoreChip<const NUM_LIMBS: usize, const LIMB_BITS: usize
 }
 
 impl<const NUM_LIMBS: usize, const LIMB_BITS: usize> MultiplicationCoreChip<NUM_LIMBS, LIMB_BITS> {
-    pub fn new(range_tuple_chip: SharedRangeTupleCheckerChip<2>) -> Self {
+    pub fn new(range_tuple_chip: SharedRangeTupleCheckerChip<2>, offset: usize) -> Self {
         // The RangeTupleChecker is used to range check (a[i], carry[i]) pairs where 0 <= i
         // < NUM_LIMBS. a[i] must have LIMB_BITS bits and carry[i] is the sum of i + 1 bytes
         // (with LIMB_BITS bits).
@@ -131,6 +132,7 @@ impl<const NUM_LIMBS: usize, const LIMB_BITS: usize> MultiplicationCoreChip<NUM_
         Self {
             air: MultiplicationCoreAir {
                 bus: *range_tuple_chip.bus(),
+                offset,
             },
             range_tuple_chip,
         }
@@ -166,7 +168,7 @@ where
     ) -> Result<(AdapterRuntimeContext<F, I>, Self::Record)> {
         let Instruction { opcode, .. } = instruction;
         assert_eq!(
-            MulOpcode::from_usize(opcode.local_opcode_idx(MulOpcode::CLASS_OFFSET)),
+            MulOpcode::from_usize(opcode.local_opcode_idx(self.air.offset)),
             MulOpcode::MUL
         );
 
@@ -190,10 +192,7 @@ where
     }
 
     fn get_opcode_name(&self, opcode: usize) -> String {
-        format!(
-            "{:?}",
-            MulOpcode::from_usize(opcode - MulOpcode::CLASS_OFFSET)
-        )
+        format!("{:?}", MulOpcode::from_usize(opcode - self.air.offset))
     }
 
     fn generate_trace_row(&self, row_slice: &mut [F], record: Self::Record) {

extensions/rv32im/circuit/src/mul/tests.rs

@@ -57,7 +57,7 @@ fn run_rv32_mul_rand_test(num_ops: usize) {
             tester.program_bus(),
             tester.memory_bridge(),
         ),
-        MultiplicationCoreChip::new(range_tuple_checker.clone()),
+        MultiplicationCoreChip::new(range_tuple_checker.clone(), MulOpcode::CLASS_OFFSET),
         tester.offline_memory_mutex_arc(),
     );
 
@@ -132,7 +132,7 @@ fn run_rv32_mul_negative_test(
             vec![None],
             ExecutionBridge::new(tester.execution_bus(), tester.program_bus()),
         ),
-        MultiplicationCoreChip::new(range_tuple_chip.clone()),
+        MultiplicationCoreChip::new(range_tuple_chip.clone(), MulOpcode::CLASS_OFFSET),
         tester.offline_memory_mutex_arc(),
     );
 

extensions/rv32im/circuit/src/shift/core.rs

@@ -55,6 +55,7 @@ pub struct ShiftCoreCols<T, const NUM_LIMBS: usize, const LIMB_BITS: usize> {
 pub struct ShiftCoreAir<const NUM_LIMBS: usize, const LIMB_BITS: usize> {
     pub bitwise_lookup_bus: BitwiseOperationLookupBus,
     pub range_bus: VariableRangeCheckerBus,
+    pub offset: usize,
 }
 
 impl<F: Field, const NUM_LIMBS: usize, const LIMB_BITS: usize> BaseAir<F>
@@ -232,7 +233,7 @@ where
     }
 
     fn start_offset(&self) -> usize {
-        ShiftOpcode::CLASS_OFFSET
+        self.offset
     }
 }
 
@@ -263,12 +264,14 @@ impl<const NUM_LIMBS: usize, const LIMB_BITS: usize> ShiftCoreChip<NUM_LIMBS, LI
     pub fn new(
         bitwise_lookup_chip: SharedBitwiseOperationLookupChip<LIMB_BITS>,
         range_checker_chip: SharedVariableRangeCheckerChip,
+        offset: usize,
     ) -> Self {
         assert_eq!(NUM_LIMBS % 2, 0, "Number of limbs must be divisible by 2");
         Self {
             air: ShiftCoreAir {
                 bitwise_lookup_bus: bitwise_lookup_chip.bus(),
                 range_bus: range_checker_chip.bus(),
+                offset,
             },
             bitwise_lookup_chip,
             range_checker_chip,
@@ -293,8 +296,7 @@ where
         reads: I::Reads,
     ) -> Result<(AdapterRuntimeContext<F, I>, Self::Record)> {
         let Instruction { opcode, .. } = instruction;
-        let shift_opcode =
-            ShiftOpcode::from_usize(opcode.local_opcode_idx(ShiftOpcode::CLASS_OFFSET));
+        let shift_opcode = ShiftOpcode::from_usize(opcode.local_opcode_idx(self.air.offset));
 
         let data: [[F; NUM_LIMBS]; 2] = reads.into();
         let b = data[0].map(|x| x.as_canonical_u32());
@@ -334,10 +336,7 @@ where
     }
 
     fn get_opcode_name(&self, opcode: usize) -> String {
-        format!(
-            "{:?}",
-            ShiftOpcode::from_usize(opcode - ShiftOpcode::CLASS_OFFSET)
-        )
+        format!("{:?}", ShiftOpcode::from_usize(opcode - self.air.offset))
     }
 
     fn generate_trace_row(&self, row_slice: &mut [F], record: Self::Record) {

extensions/rv32im/circuit/src/shift/tests.rs

@@ -57,6 +57,7 @@ fn run_rv32_shift_rand_test(opcode: ShiftOpcode, num_ops: usize) {
         ShiftCoreChip::new(
             bitwise_chip.clone(),
             tester.memory_controller().borrow().range_checker.clone(),
+            ShiftOpcode::CLASS_OFFSET,
         ),
         tester.offline_memory_mutex_arc(),
     );
@@ -150,7 +151,11 @@ fn run_rv32_shift_negative_test(
             vec![None],
             ExecutionBridge::new(tester.execution_bus(), tester.program_bus()),
         ),
-        ShiftCoreChip::new(bitwise_chip.clone(), range_checker_chip.clone()),
+        ShiftCoreChip::new(
+            bitwise_chip.clone(),
+            range_checker_chip.clone(),
+            ShiftOpcode::CLASS_OFFSET,
+        ),
         tester.offline_memory_mutex_arc(),
     );