This project covers the implementation of a 6-bit prefix adder, using the Verilog HDL and Qflow suite.
For more details see the detailed documentation (polish).
This repository has been archived by the owner on Sep 7, 2024. It is now read-only.
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6-bit prefix adder implemented via Verilog HDL.
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majabojarska/verilog-prefix-adder
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6-bit prefix adder implemented via Verilog HDL.
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