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covering right shift, and add user code tests
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ghehg committed Oct 18, 2024
1 parent aa45ae2 commit 8e8bb63
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Showing 3 changed files with 40 additions and 2 deletions.
6 changes: 5 additions & 1 deletion clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -2802,7 +2802,11 @@ class CIRShiftOpLowering
if (op.getIsShiftleft())
rewriter.replaceOpWithNewOp<mlir::LLVM::ShlOp>(op, llvmTy, val, amt);
else {
if (cirValTy.isUnsigned())
bool isUnSigned =
cirValTy ? !cirValTy.isSigned()
: !mlir::cast<mlir::cir::IntType>(cirValVTy.getEltType())
.isSigned();
if (isUnSigned)
rewriter.replaceOpWithNewOp<mlir::LLVM::LShrOp>(op, llvmTy, val, amt);
else
rewriter.replaceOpWithNewOp<mlir::LLVM::AShrOp>(op, llvmTy, val, amt);
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18 changes: 17 additions & 1 deletion clang/test/CIR/CodeGen/vectype.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@ typedef double vd2 __attribute__((vector_size(16)));
typedef long long vll2 __attribute__((vector_size(16)));
typedef unsigned short vus2 __attribute__((vector_size(4)));

void vector_int_test(int x) {
void vector_int_test(int x, unsigned short usx) {

// Vector constant.
vi4 a = { 1, 2, 3, 4 };
Expand Down Expand Up @@ -102,6 +102,22 @@ void vector_int_test(int x) {
// CHECK: %{{[0-9]+}} = cir.vec.shuffle(%{{[0-9]+}}, %{{[0-9]+}} : !cir.vector<!s32i x 4>) [#cir.int<7> : !s64i, #cir.int<5> : !s64i, #cir.int<3> : !s64i, #cir.int<1> : !s64i] : !cir.vector<!s32i x 4>
vi4 v = __builtin_shufflevector(a, b);
// CHECK: %{{[0-9]+}} = cir.vec.shuffle.dynamic %{{[0-9]+}} : !cir.vector<!s32i x 4>, %{{[0-9]+}} : !cir.vector<!s32i x 4>

// Shifts
vi4 w = a << b;
// CHECK: %{{[0-9]+}} = cir.shift(left, {{%.*}} : !cir.vector<!s32i x 4>,
// CHECK-SAME: {{%.*}} : !cir.vector<!s32i x 4>) -> !cir.vector<!s32i x 4>
vi4 y = a >> b;
// CHECK: %{{[0-9]+}} = cir.shift( right, {{%.*}} : !cir.vector<!s32i x 4>,
// CHECK-SAME: {{%.*}} : !cir.vector<!s32i x 4>) -> !cir.vector<!s32i x 4>

vus2 z = { usx, usx };
// CHECK: %{{[0-9]+}} = cir.vec.create(%{{[0-9]+}}, %{{[0-9]+}} : !u16i, !u16i) : !cir.vector<!u16i x 2>
vus2 zamt = { 3, 4 };
// CHECK: %{{[0-9]+}} = cir.const #cir.const_vector<[#cir.int<3> : !u16i, #cir.int<4> : !u16i]> : !cir.vector<!u16i x 2>
vus2 zzz = z >> zamt;
// CHECK: %{{[0-9]+}} = cir.shift( right, {{%.*}} : !cir.vector<!u16i x 2>,
// CHECK-SAME: {{%.*}} : !cir.vector<!u16i x 2>) -> !cir.vector<!u16i x 2>
}

void vector_double_test(int x, double y) {
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18 changes: 18 additions & 0 deletions clang/test/CIR/Lowering/vectype.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -219,6 +219,24 @@ void vector_int_test(int x) {
// CHECK: %[[#svQ:]] = llvm.extractelement %[[#sv_a]][%[[#svP:]] : i32] : vector<4xi32>
// CHECK: %[[#svR:]] = llvm.insertelement %[[#svQ]], %[[#svN]][%[[#svO]] : i64] : vector<4xi32>
// CHECK: llvm.store %[[#svR]], %[[#sv_v:]] {alignment = 16 : i64} : vector<4xi32>, !llvm.ptr

// Shifts
vi4 w = a << b;
// CHECK: %[[#T198:]] = llvm.load %[[#T3]] {alignment = 16 : i64} : !llvm.ptr -> vector<4xi32>
// CHECK: %[[#T199:]] = llvm.load %[[#T5]] {alignment = 16 : i64} : !llvm.ptr -> vector<4xi32>
// CHECK: %{{[0-9]+}} = llvm.shl %[[#T198]], %[[#T199]] : vector<4xi32>
vi4 y = a >> b;
// CHECK: %[[#T201:]] = llvm.load %[[#T3]] {alignment = 16 : i64} : !llvm.ptr -> vector<4xi32>
// CHECK: %[[#T202:]] = llvm.load %[[#T5]] {alignment = 16 : i64} : !llvm.ptr -> vector<4xi32>
// CHECK: %{{[0-9]+}} = llvm.ashr %[[#T201]], %[[#T202]] : vector<4xi32>

vus2 z = { (unsigned short)x, (unsigned short)x };
vus2 zamt = { 3, 4 };
// CHECK: %[[#T219:]] = llvm.mlir.constant(dense<[3, 4]> : vector<2xi16>) : vector<2xi16>
// CHECK: llvm.store %[[#T219]], %[[#AMT_SAVE:]] {alignment = 4 : i64} : vector<2xi16>
// CHECK: %[[#T221:]] = llvm.load %[[#AMT_SAVE]] {alignment = 4 : i64} : !llvm.ptr -> vector<2xi16>
vus2 zzz = z >> zamt;
// CHECK: %{{[0-9]+}} = llvm.lshr %{{[0-9]+}}, %[[#T221]] : vector<2xi16>
}

void vector_double_test(int x, double y) {
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