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Issues: google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0

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10 Open 6 Closed
10 Open 6 Closed
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Issues list

Technology LEF files have incorrect CPERSQDIST
#30 opened Dec 9, 2022 by RTimothyEdwards
15
.spice netlist is messed up due to label placement
#25 opened Nov 25, 2022 by AL-255
1
Gate level verilog modules are horribly broken and unusable
#24 opened Nov 20, 2022 by RTimothyEdwards
@mkkassem @atorkmabrains
16
Missing Resistance for vias in tech lef
#19 opened Sep 4, 2022 by kareefardi
@mohanad0mohamed
14
Set up readthedocs pull request rendering
#13 opened Aug 10, 2022 by mithro
1
Figure out what is going on with the fill schematic rendering
#12 opened Aug 10, 2022 by mithro
Figure out how to fix the flip flop schematic rendering
#11 opened Aug 10, 2022 by mithro
Figure out how to fix the buffers schematic rendering
#10 opened Aug 10, 2022 by mithro
Add verilog test benches for each of the standard cells.
#4 opened Jul 20, 2022 by mithro
CI should check that the standard cells pass the GF180MCU DRC rules
#2 opened Jul 20, 2022 by mithro
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