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Update the names of files under docs/analog/model_parameters/LV/tables_clear #51

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12 changes: 6 additions & 6 deletions docs/analog/model_parameters/LV/LV_1_5_1.rst
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Expand Up @@ -6,16 +6,16 @@ The MOSFET instance parameters shall be used in the netlist are described below
.. csv-table::
:file: tables_clear/09_MOSFET_Instance.csv

1.5.1.1 LV NMOS (3.3V) and LV PMOS (3.3V) & NMOS SAB (3.3V) and PMOS SAB (3.3V)
"""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""
1.5.1.1 LV nfet_03v3 (3.3V) and pfet_03v3 (3.3V) & nfet_03v3_dss (3.3V) and pfet_03v3_dss (3.3V)
"""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""

.. csv-table::
:file: tables_clear/10_LV_NMOS.csv
:file: tables_clear/10_nfet_pfet_03v3_models.csv


1.5.1.2 MV NMOS (5V/6V), MV PMOS (5V/6V), NMOS SAB (5V/6V), PMOS SAB (5V/6V) and native NMOS (6V)
"""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""
1.5.1.2 MV nfet_06v0 (5V/6V), pfet_06v0 (5V/6V), nfet_06v0_dss (5V/6V), pfet_06v0_dss (5V/6V) and nfet_06v0_nvt (6V)
"""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""

.. csv-table::
:file: tables_clear/11_MV_NMOS.csv
:file: tables_clear/11_nfet_pfet_06v0_models.csv

6 changes: 3 additions & 3 deletions docs/analog/model_parameters/LV/LV_2_2.rst
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Expand Up @@ -5,13 +5,13 @@

During a FET netlist call, users should use design dimension for W and L, not effective width and length. In this release, the BSIM model parameter Lmin is set to the nominal drawn gate length. This may cause warnings to be generated during corner simulations when the biased gate length becomes less than Lmin. This warning has no effect on the simulation results.

2.2.1 LV NMOS and LV PMOS (3.3V)
................................
2.2.1 nfet_03v3 and pfet_03v3 (3.3V)
......................................

Device size (unit - um)

.. csv-table::
:file: tables_clear/16_LV_NPMOS.csv
:file: tables_clear/16_nfet_pfet_03v3_dimensions.csv

.. note::

Expand Down
17 changes: 10 additions & 7 deletions docs/analog/model_parameters/LV/LV_2_5.rst
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Expand Up @@ -24,14 +24,14 @@ where
..................................

.. csv-table::
:file: tables_clear/19_mos_3p3.csv
:file: tables_clear/19_nfet_pfet_03v3.csv


2.5.2 NMOS 3p3 SAB PMOS 3p3 SAB
...............................
2.5.2 nfet_03v3_dss and pfet_03v3_dss
.......................................

.. csv-table::
:file: tables_clear/20_MOS_3p3_SAB.csv
:file: tables_clear/20_nfet_pfet_03v3_dss.csv

.. note::

Expand All @@ -43,7 +43,10 @@ where
................................

.. csv-table::
:file: tables_clear/21_mos_6p0.csv
:file: tables_clear/21_nfet_pfet_06v0.csv

.. csv-table::
:file: tables_clear/21_nfet_pfet_06v0_dss.csv

.. note::

Expand All @@ -55,8 +58,8 @@ where
................................

.. csv-table::
:file: tables_clear/22_mos_6p0_1.csv
:file: tables_clear/22_nfet_pfet_06v0.csv

.. csv-table::
:file: tables_clear/22_mos_6p0_2.csv
:file: tables_clear/22_nfet_pfet_06v0_dss.csv

0 ...parameters/LV/tables_clear/10_LV_NMOS.csv → ...tables_clear/10_nfet_pfet_03v3_models.csv
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0 ...parameters/LV/tables_clear/11_MV_NMOS.csv → ...tables_clear/11_nfet_pfet_06v0_models.csv
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0 ...arameters/LV/tables_clear/16_LV_NPMOS.csv → ...es_clear/16_nfet_pfet_03v3_dimensions.csv
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0 ...parameters/LV/tables_clear/19_mos_3p3.csv → ...ers/LV/tables_clear/19_nfet_pfet_03v3.csv
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0 ...meters/LV/tables_clear/20_MOS_3p3_SAB.csv → ...LV/tables_clear/20_nfet_pfet_03v3_dss.csv
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0 ...parameters/LV/tables_clear/21_mos_6p0.csv → ...ers/LV/tables_clear/21_nfet_pfet_06v0.csv
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0 ...rameters/LV/tables_clear/21_mos_6p0_2.csv → ...LV/tables_clear/21_nfet_pfet_06v0_dss.csv
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0 ...rameters/LV/tables_clear/22_mos_6p0_1.csv → ...s/LV/tables_clear/22_nfet_pfet_06v0_1.csv
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0 ...rameters/LV/tables_clear/22_mos_6p0_2.csv → ...s/LV/tables_clear/22_nfet_pfet_06v0_2.csv
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