Fix latest pylint issues

gezalore · Sep 19, 2024 · 3676768 · 3676768
1 parent dd95e03
commit 3676768
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Showing 3 changed files with 6 additions and 3 deletions.
diff --git a/bin/verilator_profcfunc b/bin/verilator_profcfunc
@@ -135,8 +135,7 @@ def profcfunc(filename):
 
     design_width = 1
     for func, func_item in vfuncs.items():
-        if design_width < len(func_item['design']):
-            design_width = len(func_item['design'])
+        design_width = max(design_width, len(func_item['design']))
 
     print("Verilog code profile:")
     print("   These are split into three categories:")

diff --git a/src/astgen b/src/astgen
@@ -852,6 +852,10 @@ def write_type_tests(prefix, nodeList):
             base = "DfgVertex"
             variable = "vtxp"
             enum = "VDfgType"
+        else:
+            base = None
+            variable = None
+            enum = None
         for node in nodeList:
             fh.write(
                 "template<> inline bool {b}::privateTypeTest<{p}{n}>(const {b}* {v}) {{ ".format(

diff --git a/src/bisonpre b/src/bisonpre
@@ -16,7 +16,7 @@ def process():
     unlink_outputs()
 
     bison_version_check()
-    supports_report = Bison_Version >= 2.3
+    supports_report = Bison_Version >= 2.3  # pylint: disable=possibly-used-before-assignment
     # supports_counter_examples = Bison_Version >= 3.8
 
     clean_input(Args.input, tmp_prefix() + ".y")