Negative SInt values show up as Xs in VCD output, other discrepancies between firrtl and verilator VCD traces

[rimasaviz]

Negative valued SInts are not handled properly when generating VCD traces - they show up as Xs. Looking at VCD.scala (the Change case class), it appears that negative values associated with a wire are always interpreted as uninitialized values.

I've attached a screenshot showing VCD traces produced by firrtl (top) and Verilator when running the same test. SInts that have the MSB set (in the Verilator output) show up as X's in the firrtl output. Also, notice that the timing of the reset and io_din_valid signals are different... this would have caused the firrtl version of the test to fail if it weren't for the "init" signal which initializes the DUT to a known state... not cool!

[chick]

This seems to be two different issues. The negative number is clearly wrong, I'm amazed we've gone this long without this coming up. The interpreter does not do x propagation, it only has a limited concept of uninitialized. This display issue should be easy to fix.

I have created a separate Issue #118 for figuring out the reset issue. I'm not as sure how easy it is to fix, (mostly it is more likely to break other things than fixing the display issue).

[chick]

Was fixed in PR #118