Merge pull request #7 from esp-rs/cpu-configurations

Move CPU configs behind features, add features for lx6 and lx106

Cargo.toml

@@ -1,20 +1,33 @@
 [package]
-name = "xtensa-lx6"
-version = "0.2.0"
-description = "Low level access for xtensa lx6 processors and peripherals"
+name = "xtensa-lx"
+version = "0.3.0"
+description = "Low level access for xtensa lx processors and peripherals"
 categories = ["embedded", "hardware-support", "no-std"]
-keywords = ["xtensa", "lx6", "register", "peripheral"]
+keywords = ["xtensa", "lx", "register", "peripheral"]
 license = "MIT OR Apache-2.0"
 readme = "README.md"
-repository = "https://github.com/esp-rs/xtensa-lx6"
+repository = "https://github.com/esp-rs/xtensa-lx"
 authors = ["Scott Mabin <[email protected]>", "Arjan Mels <[email protected]>"]
 edition = "2018"
-links = "xtensa-lx6" # prevent multiple versions of this crate to be linked together
-
-# See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html
+links = "xtensa-lx" # prevent multiple versions of this crate to be linked together
 
 [dependencies]
 r0 = "1.0.0"
 bare-metal = { version = "0.2.0", features = ["const-fn"] }
 spin = "0.5.2"
 mutex-trait = "0.2"
+
+[features]
+lx6 = ["ccompare0", "ccompare1", "ccompare2", "ccount"]
+lx106 = ["ccompare0", "ccount"]
+
+# CPU configurations, taken from: https://github.com/espressif/xtensa-overlays
+
+# Timers up to 4
+ccompare0 = []
+ccompare1 = []
+ccompare2 = []
+ccompare3 = []
+
+# ccount
+ccount = []

LICENSE-MIT

@@ -1,4 +1,4 @@
-Copyright 2019-2020 Contributors to xtensa-lx6-rt
+Copyright 2019-2020 Contributors to xtensa-lx-rt
 
 Permission is hereby granted, free of charge, to any
 person obtaining a copy of this software and associated

README.md

@@ -1,6 +1,11 @@
-# `xtensa-lx6`
+# `xtensa-lx`
 
-Low level access to xtensa lx6 processors. These processors are used in the ESP32 SoC's.
+Low level access to xtensa lx processors. This crate currently supports the following CPU's:
+
+| Feature        | Description                                    |
+|----------------|------------------------------------------------|
+|   `lx6`        | The processors are used in the ESP32 SoC's.    |
+|   `lx106`      | The processors are used in the ESP8266 SoC's.  |
 
 ## License
 

src/macros.rs

@@ -8,7 +8,7 @@
 /// # Example
 ///
 /// ``` no_run
-/// use xtensa_lx6::singleton;
+/// use xtensa_lx::singleton;
 ///
 /// fn main() {
 ///     // OK if `main` is executed only once

src/timer.rs

@@ -1,24 +1,36 @@
 //! Xtensa internal timers
 
+#[cfg(feature = "ccompare0")]
 #[inline]
 pub fn get_ccompare0() -> u32 {
     let x: u32;
     unsafe { llvm_asm!("rsr.ccompare0 $0" : "=r"(x) ::: "volatile" ) };
     x
 }
+#[cfg(feature = "ccompare1")]
 #[inline]
 pub fn get_ccompare1() -> u32 {
     let x: u32;
     unsafe { llvm_asm!("rsr.ccompare1 $0" : "=r"(x) ::: "volatile" ) };
     x
 }
+#[cfg(feature = "ccompare2")]
 #[inline]
 pub fn get_ccompare2() -> u32 {
     let x: u32;
     unsafe { llvm_asm!("rsr.ccompare2 $0" : "=r"(x) ::: "volatile" ) };
     x
 }
 
+#[cfg(feature = "ccompare3")]
+#[inline]
+pub fn get_ccompare3() -> u32 {
+    let x: u32;
+    unsafe { llvm_asm!("rsr.ccompare3 $0" : "=r"(x) ::: "volatile" ) };
+    x
+}
+
+#[cfg(feature = "ccompare0")]
 #[inline]
 pub fn set_ccompare0(val: u32) {
     unsafe {
@@ -28,6 +40,7 @@ pub fn set_ccompare0(val: u32) {
         " :: "r"(val):::: "volatile" )
     };
 }
+#[cfg(feature = "ccompare1")]
 #[inline]
 pub fn set_ccompare1(val: u32) {
     unsafe {
@@ -37,6 +50,7 @@ pub fn set_ccompare1(val: u32) {
         " :: "r"(val):::: "volatile" )
     };
 }
+#[cfg(feature = "ccompare2")]
 #[inline]
 pub fn set_ccompare2(val: u32) {
     unsafe {
@@ -46,8 +60,19 @@ pub fn set_ccompare2(val: u32) {
         " :: "r"(val):::: "volatile" )
     };
 }
+#[cfg(feature = "ccompare3")]
+#[inline]
+pub fn set_ccompare3(val: u32) {
+    unsafe {
+        llvm_asm!("
+        wsr.ccompare3 $0
+        isync
+        " :: "r"(val):::: "volatile" )
+    };
+}
 
 /// Get the core cycle count
+#[cfg(feature = "ccount")]
 #[inline]
 pub fn get_cycle_count() -> u32 {
     let x: u32;
@@ -56,6 +81,7 @@ pub fn get_cycle_count() -> u32 {
 }
 
 /// cycle accurate delay using the cycle counter register
+#[cfg(feature = "ccount")]
 #[inline]
 pub fn delay(clocks: u32) {
     let start = get_cycle_count();